GPIO pulse generated - inconsistent width

marsal64
Posts: 4
Joined: Mon Jan 24, 2022 7:30 pm

GPIO pulse generated - inconsistent width

Postby marsal64 » Thu Jun 20, 2024 11:44 am

Hi,

using ESP32-S3 at 160MHz, I run once per some seconds the code:

Code: Select all

gpio_set_level(GPIO_NUM_36, 1);
gpio_set_level(GPIO_NUM_36, 0);
My app runs WiFi, UART and two other lightweight FreeRTOS tasks.

I observe non-consistent width of the "pulse" I generate on GPIO_NUM_36 pin:
Typically: 6.6uS
Sometimes: 1.275uS
Rarely: 3.3625uS

Could please anybody explain what is happening here?

Thank you

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ok-home
Posts: 78
Joined: Sun May 02, 2021 7:23 pm
Location: Russia Novosibirsk
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Re: GPIO pulse generated - inconsistent width

Postby ok-home » Thu Jun 20, 2024 1:45 pm

Hi
bitbang on esp32 gives unpredictable results
- interrupts (wifi,freertos...)
- cache misses
- .....
as an example simple code

Code: Select all

 
 gpio_set_level(GPIO_BLINK, 1); 
 gpio_set_level(GPIO_BLINK, 0); 
 .........
 gpio_set_level(GPIO_BLINK, 1); 
 gpio_set_level(GPIO_BLINK, 0); 
 ............ 
 GPIO.out_w1ts = mask; 
 GPIO.out_w1tc = mask; 
 ........... 
 GPIO.out_w1ts = mask; 
 GPIO.out_w1tc = mask; 

when code in flash memory and IRAM and the process of swapping cache from flash memory
bitbang.JPG
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MicroController
Posts: 1736
Joined: Mon Oct 17, 2022 7:38 pm
Location: Europe, Germany

Re: GPIO pulse generated - inconsistent width

Postby MicroController » Thu Jun 20, 2024 2:11 pm

marsal64 wrote:
Thu Jun 20, 2024 11:44 am

Code: Select all

gpio_set_level(GPIO_NUM_36, 1);
gpio_set_level(GPIO_NUM_36, 0);
Could please anybody explain what is happening here?
Likely: Caching, possibly: synchronization of the CPU with the APB and the GPIO peripheral.
You can look into Dedicated GPIO to improve the latter, and put code into IRAM to avoid cache issues.

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