ESP32 Forum

In reference to the demo code <uart_async_rxtxtasks> installed into VSC with ESP32-H2-Mini1 device. I note from datasheet the FIFO is 260 Byte in RAM shared between UART0 and UART1. I have setup UART1 for general serial comm of my design while UART0 is used for flashing and monitor role.
I note the demo code below where the BUF_SIZE is 1024, so we have 2048 in TX and 2048 in RX; how did they manage to fit into 260 Byte UART/FIFO RAM? without reporting an error?

uart_config_t uart_config =
{
.baud_rate = 115200,
.data_bits = UART_DATA_8_BITS,
.parity = UART_PARITY_DISABLE,
.stop_bits = UART_STOP_BITS_1,
.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
.source_clk = UART_SCLK_DEFAULT,
};
//Install UART driver, and get the queue.
uart_driver_install(EX_UART_NUM, BUF_SIZE * 2, BUF_SIZE * 2, 20, &uart1_queue, 0);
uart_param_config(EX_UART_NUM, &uart_config);

Please confirm if the above BUF_SIZE code setting is wrong

How to check how UART RAM is consumed between UART0 and UART1.

Between the hardware FIFO and the application, the UART driver provides an additional buffer (ring buffer) in normal RAM (heap).
For this 'software buffer' you can request any size you want, limited only by the available heap memory.