ESP32S3 flash write & cache panic handler issue

[Demirug]

My code is mostly irq driven (LCD, I2S & timer). The code for all these irq handlers is flagged with IRAM_ATTR. The irqs are allocated with the ESP_INTR_FLAG_IRAM flag to ensure they keep running all the time. As most of the code is flagged to be loaded into memory and there are not much data both I and D cache are set to 16KB.

In irregular intervals a task will write some data to the flash memory. Beside this it is mostly just waiting in a vTaskDelay.

This worked fine until today. Now I am getting

"Guru Meditation Error: Core 1 panic'ed (Cache disabled but cached memory region accessed)"

while the flash write is running (on core 0) in the irq handler for the timer. I checked the callstack and all functions are as expected in the iRAM.

The main change was that I needed to allocate some more memory. Based on heap_caps_print_heap_info I am now using this block, too:

heap_init: At 3C000000 len 00004000 (16 KiB): DRAM

In the crash message from the panic handler one of the registers actually contains an address in this area every time.

The memory map says that this address is actually for the flash or the psram. But my understanding is that if only 16KB memory is used the start of this block is mapped to some of the unused cache memory.

I might need to do some more tests but maybe somebody knows this already. Is this a known limitation that memory in this area could not be used while writing to the flash?