ESP32S3 : Is it possible to trigger a CPU software interrupt from the RISCV ULP ?
Posted: Mon Mar 11, 2024 11:02 am
Good morning,
I have seen in the Esp32S3 reference manual that there were software innterrupts that can be triggered when writting to special
registers.
Do you think it is possible to trigger CPU0 software interrupt from the RISCV ULP ?
My goal would be to do an action in the CPU0 (Using an interrupt) as soon as the RISCV Copro request it.
If the answer is Yes, do you have any example or something please ?
Thank you for your help,
this is really important.
Best regards,
Thomas TRUILHE
I have seen in the Esp32S3 reference manual that there were software innterrupts that can be triggered when writting to special
registers.
Do you think it is possible to trigger CPU0 software interrupt from the RISCV ULP ?
My goal would be to do an action in the CPU0 (Using an interrupt) as soon as the RISCV Copro request it.
If the answer is Yes, do you have any example or something please ?
Thank you for your help,
this is really important.
Best regards,
Thomas TRUILHE