5.1.2 to 5.2 migration- Interrupt Allocation Issue
Posted: Fri Feb 23, 2024 4:17 pm
Hello,
We are upgrading our IDF from 5.1.2 to 5.2
The only change we had to make for the build to succeed is the SPI(using SPI3) .isr_cpu_id from INTR_CPU_ID_AUTO to ESP_INTR_CPU_AFFINITY_AUTO
------5.1.2 SPI configuration----
------ 5.2 ----
In the project, we are also using the MCPWM module, which uses the PWM interrupt. When 5.2 is run, we get the following interrupt allocation error:
The esp_intr_dump() is below:
If I change the SPI ISR to .isr_cpu_id = ESP_INTR_CPU_AFFINITY_1, the issue goes away. Has the interrupt allocation method changed between 5.1.2 and 5.2? The migration doc does not mention anything about interrupt allocation.
We are upgrading our IDF from 5.1.2 to 5.2
The only change we had to make for the build to succeed is the SPI(using SPI3) .isr_cpu_id from INTR_CPU_ID_AUTO to ESP_INTR_CPU_AFFINITY_AUTO
------5.1.2 SPI configuration----
Code: Select all
spi {
/* TODO Change to CONFIG_*/
.mosi_io_num = GPIO_NUM_11,
.miso_io_num = GPIO_NUM_10,
.sclk_io_num = GPIO_NUM_12,
.quadwp_io_num = -1,
.quadhd_io_num = -1,
.data4_io_num = -1,
.data5_io_num = -1,
.data6_io_num = -1,
.data7_io_num = -1,
.max_transfer_sz = 16,
.flags = 0,
.isr_cpu_id = INTR_CPU_ID_AUTO,
.intr_flags = 0,
},
Code: Select all
spi {
/* TODO Change to CONFIG_*/
.mosi_io_num = GPIO_NUM_11,
.miso_io_num = GPIO_NUM_10,
.sclk_io_num = GPIO_NUM_12,
.quadwp_io_num = -1,
.quadhd_io_num = -1,
.data4_io_num = -1,
.data5_io_num = -1,
.data6_io_num = -1,
.data7_io_num = -1,
.max_transfer_sz = 16,
.flags = 0,
.isr_cpu_id = ESP_INTR_CPU_AFFINITY_AUTO,
.intr_flags = 0,
},
Code: Select all
E (1795) intr_alloc: No free interrupt inputs for PWM0 interrupt (flags 0xD0E)
HINT: For troubleshooting instructions related to interrupt allocation, run 'idf.py docs -sp api-reference/system/intr_alloc.html'
E (1795) mcpwm: mcpwm_timer_register_event_callbacks(223): install interrupt service for timer failed
Code: Select all
CPU 0 interrupt status:
Int Level Type Status
0 1 Level Reserved
1 1 Level Reserved
2 1 Level Used: RTC_CORE
3 1 Level Used: SYSTIMER_TARGET2
4 1 Level Reserved
5 1 Level Reserved
6 1 Level CPU-internal
7 1 Level CPU-internal
8 1 Level Reserved
9 1 Level Used: FROM_CPU_INTR0
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Used: SYSTIMER_TARGET0
13 1 Level Used: TG0_WDT_LEVEL
14 7 Level Reserved
15 3 Level CPU-internal
16 5 Level CPU-internal
17 1 Level Used: AES
18 1 Level Used: I2C_EXT0
19 2 Level Used: USB_SERIAL_JTAG
20 2 Level Used: I2C_EXT1
21 2 Level Used: GPIO
22 3 Edge Reserved
23 3 Level Used: SPI3
24 4 Level Reserved
25 4 Level Reserved
26 5 Level Free (not general-use)
27 3 Level Reserved
28 4 Edge Free (not general-use)
29 3 Level CPU-internal
30 4 Edge Reserved
31 5 Level Reserved
CPU 1 interrupt status:
Int Level Type Status
0 1 Level Reserved
1 1 Level Reserved
2 1 Level Used: FROM_CPU_INTR1
3 1 Level Used: SYSTIMER_TARGET1
4 1 Level Free
5 1 Level Reserved
6 1 Level CPU-internal
7 1 Level CPU-internal
8 1 Level Reserved
9 1 Level Free
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Free
13 1 Level Free
14 7 Level Reserved
15 3 Level CPU-internal
16 5 Level CPU-internal
17 1 Level Free
18 1 Level Free
19 2 Level Free
20 2 Level Free
21 2 Level Free
22 3 Edge Free (not general-use)
23 3 Level Free
24 4 Level Free (not general-use)
25 4 Level Reserved
26 5 Level Reserved
27 3 Level Reserved
28 4 Edge Free (not general-use)
29 3 Level CPU-internal
30 4 Edge Reserved
31 5 Level Reserved
Interrupts available for general use: 10
Shared interrupts: 0
Code: Select all
CPU 0 interrupt status:
Int Level Type Status
0 1 Level Reserved
1 1 Level Reserved
2 1 Level Used: RTC_CORE
3 1 Level Used: SYSTIMER_TARGET2
4 1 Level Reserved
5 1 Level Reserved
6 1 Level CPU-internal
7 1 Level CPU-internal
8 1 Level Reserved
9 1 Level Used: FROM_CPU_INTR0
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Used: SYSTIMER_TARGET0
13 1 Level Used: TG0_WDT_LEVEL
14 7 Level Reserved
15 3 Level CPU-internal
16 5 Level CPU-internal
17 1 Level Used: AES
18 1 Level Used: I2C_EXT0
19 2 Level Used: USB_SERIAL_JTAG
20 2 Level Used: I2C_EXT1
21 2 Level Used: GPIO
22 3 Edge Reserved
23 3 Level Free
24 4 Level Reserved
25 4 Level Reserved
26 5 Level Free (not general-use)
27 3 Level Reserved
28 4 Edge Free (not general-use)
29 3 Level CPU-internal
30 4 Edge Reserved
31 5 Level Reserved
CPU 1 interrupt status:
Int Level Type Status
0 1 Level Reserved
1 1 Level Reserved
2 1 Level Used: FROM_CPU_INTR1
3 1 Level Used: SYSTIMER_TARGET1
4 1 Level Used: SPI3
5 1 Level Reserved
6 1 Level CPU-internal
7 1 Level CPU-internal
8 1 Level Reserved
9 1 Level Shared: PWM0
10 1 Edge Free (not general-use)
11 3 Level CPU-internal
12 1 Level Free
13 1 Level Free
14 7 Level Reserved
15 3 Level CPU-internal
16 5 Level CPU-internal
17 1 Level Free
18 1 Level Free
19 2 Level Free
20 2 Level Free
21 2 Level Free
22 3 Edge Free (not general-use)
23 3 Level Free
24 4 Level Free (not general-use)
25 4 Level Reserved
26 5 Level Reserved
27 3 Level Reserved
28 4 Edge Free (not general-use)
29 3 Level CPU-internal
30 4 Edge Reserved
31 5 Level Reserved
Interrupts available for general use: 9
Shared interrupts: 1