logic analyser result: https://imgur.com/a/p8ruCaL
However, when I set the i2s slot config to I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_24BIT, I2S_SLOT_MODE_STEREO) , I get nothing but garbled data. But when I set the data bit width to 32bit, it works without any issue, and the I2S read result is consistent with my logic analyzer's result.
So, why? Espressif's official documentation seems to indicate that data bit width is the width of the actual data, and can be less than the slot bit width. One would assume that, in my case, according to the image at https://docs.espressif.com/projects/esp ... ndard-mode , data_bit_width = 24, and slot_bit_width = 32.
My I2S configuration:
- i2s_std_config_t rx_std_cfg = {
- .clk_cfg ={
- .sample_rate_hz = 48000,
- .clk_src = I2S_CLK_SRC_DEFAULT,
- .mclk_multiple = I2S_MCLK_MULTIPLE_384,
- },
- .slot_cfg =I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_32BIT, I2S_SLOT_MODE_STEREO),
- .gpio_cfg = {
- .mclk = I2S_GPIO_UNUSED, // some codecs may require mclk signal, this example doesn't need it
- .bclk = EXAMPLE_STD_BCLK_IO1,
- .ws = EXAMPLE_STD_WS_IO1,
- .dout = I2S_GPIO_UNUSED,
- .din = EXAMPLE_STD_DIN_IO1,
- .invert_flags = {
- .mclk_inv = false,
- .bclk_inv = false,
- .ws_inv = false,
- },
- },
- };