ESP32 Forum

Hi,

Is there any known issue or limitations about using UART and SPI at the same time on ESP32-WROOM-32 ?

In our application we have two configuration with SPI and UART in parallel and both lead to having the SPI communication broken.

1. ESP logging function (using UART0) calls from task running on core 0 while SPI communication is in progress on core 1. SPI is using polling mode and communication is protected with spinlock and critical sections.

2. Modbus incoming request on UART2 with SPI is running as in dot 1. Mobbus task is running on core 0.
If I set the modbus task to run on same core than SPI (I.e core 1), it works.

So it seems there's something wrong maybe in HW. I already found this topic https://esp32.com/viewtopic.php?t=28292 on the forum that looks similar.

As far as I know, those hardware components do not overlap. Unless you make them overlap (e.g. by accidentally picking the same GPIO pins for both), they should not interfere.

Hi.
No ressources are not the same.
SPI is using GPIOs 27, 32, 33 and 35
Logging (UART0) is using GPIOs 1 and 3 (U0RXD, U0TXD)
Modbus (RS485) is using GPIOs 12, 14, 25 and 26

SPI is using polling mode and communication is protected with spinlock and critical sections.
...
If I set the modbus task to run on same core than SPI (I.e core 1), it works.

Sounds like there's something wrong with the way you implemented the synchronization.

Maybe ..
But I tried different implementation. Now i use only binary mutexes to protect the spi communication on core 1.
But it is still the same the issue as soon as core 0 is using UART.

So to summarize I have:
- GPIO IRQ attached on core 1
- Task notifyed by IRQ also on core 1 doing SPI communication in polling mode.
- Modbus component on core 0

Then SPI communication is broken as soon as something happens on modbus side (UART2).
If I put modbus on core 1 -> OK.

I can have made synchronization mistake (I doubt )... but in this case, if anyone can give the right thing to do, it would be nice ?

Hi,
After further investigation, it looks that the issue is not related to SPI but about the GPIO IRQ (pin 34) used to manage the SPI communication.
SPI communication is ok (write and read operations) but tracing my code, I observe that as soon as the UART operates on core 0, the IRQ (attached to core 1) does not occur anymore for a long period.

I have try the workaround from the errata uisng HIGH_LEVEL instead of EDGE but I do still have the same problem.

Any ideas ?