Clarification on ULP co-processor REG_RD instruction
Posted: Thu Nov 23, 2017 3:41 am
Am studying the REG_RD instruction in the documentation found here:
http://esp-idf.readthedocs.io/en/latest ... l-register
In there, there is an example:
My puzzle is, that I am not seeing the match between the example instruction and its comment. To me,
Should result in:
or in other words, the ULP Co-processor register called R0 will be loaded with the 3 bits (bit 2, bit 1, bit 0) from the 32 bit word found at word index 0x120 from the base of the RTC peripheral memory. Compared to the example, we are loading 3 bits and not 4 and the positions of the bits are distinct. Might this be a typo in the example or ... and hence the question ... a failure on my part to understand a concept?
http://esp-idf.readthedocs.io/en/latest ... l-register
In there, there is an example:
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REG_RD 0x120, 2, 0 // load 4 bits: R0 = {12'b0, REG[0x120][7:4]}
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REG_RD 0x120, 2, 0
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R0 = REG[0x120][2:0]