What is the safest way of reserving, let's say 1KB of RAM in internal RAM
Posted: Wed Oct 25, 2023 12:12 pm
I saw an option in sdkconfig about IRAM reservation with a warning disclaimer.
So what is the safest way to reserve a block of RAM (for some global variables I want to store there) and be sure, such a RAM block is "invisible" to C compiler in a sense, that either heap, either stack, either anything dynamically created at runtime, either possibly any of integrated peripheral which needs RAM for proper operation, either bootloader, will never overlap that block?
If I turn that option in sdkconfig how do I obtain a pointer to the start of that block?
What are the advantages/disadvantages of making it in IRAM/RTC_FAST_RAM/RTC_SLOW_RAM ? I didn't find any documentation describing clocking operations on read/writes cycles with timings. How big is that difference in speed among those different rams?
Can all of those memories be accessed with word (2 byte) alignment or only (4 byte) aligned reads/writes?
I saw that ULP writes in RTC ram are always 4 byte aligned and two upper bytes are used to store address of instruction which accessed that location. But if I do not use ULP, are those 2 upper bytes accessible as 16 bits read/writes (avoiding masking on 32 bits read/writes) from PRO/APP CPUs?
So what is the safest way to reserve a block of RAM (for some global variables I want to store there) and be sure, such a RAM block is "invisible" to C compiler in a sense, that either heap, either stack, either anything dynamically created at runtime, either possibly any of integrated peripheral which needs RAM for proper operation, either bootloader, will never overlap that block?
If I turn that option in sdkconfig how do I obtain a pointer to the start of that block?
What are the advantages/disadvantages of making it in IRAM/RTC_FAST_RAM/RTC_SLOW_RAM ? I didn't find any documentation describing clocking operations on read/writes cycles with timings. How big is that difference in speed among those different rams?
Can all of those memories be accessed with word (2 byte) alignment or only (4 byte) aligned reads/writes?
I saw that ULP writes in RTC ram are always 4 byte aligned and two upper bytes are used to store address of instruction which accessed that location. But if I do not use ULP, are those 2 upper bytes accessible as 16 bits read/writes (avoiding masking on 32 bits read/writes) from PRO/APP CPUs?