ESP32 Forum

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#include <stdio.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "driver/gpio.h"
#include "driver/dedic_gpio.h"
#include "logic_analyzer_ws_server.h"
#include "soc/gpio_reg.h"
#include "soc/soc.h"

void dedic_task(void *p)
{
    const int bundleA_gpios[] = {6, 7,8,9,10,11,12,13};
    gpio_config_t io_conf = {
        .mode = GPIO_MODE_INPUT_OUTPUT,
        .pull_down_en = true,
    };
    uint64_t oemask = 0; // gpio mask -> enable/disable output
    for (int i = 0; i < sizeof(bundleA_gpios) / sizeof(bundleA_gpios[0]); i++)
    {
        io_conf.pin_bit_mask = 1ULL << bundleA_gpios[i];
        gpio_config(&io_conf);
        oemask |=  io_conf.pin_bit_mask; // gpio mask -> enable/disable output
    }
    // Create bundleA, output only
    dedic_gpio_bundle_handle_t bundleA = NULL;
    dedic_gpio_bundle_config_t bundleA_config = {
        .gpio_array = bundleA_gpios,
        .array_size = sizeof(bundleA_gpios) / sizeof(bundleA_gpios[0]),
        .flags = {
            .out_en = 1,
            .in_en = 1 // input mode already connected
        },
    };
    ESP_ERROR_CHECK(dedic_gpio_new_bundle(&bundleA_config, &bundleA));

// switch OEN control to register GPIO_ENABLE_W1TS_REG/REG_WRITE(GPIO_ENABLE_W1TC_REG

    for (int i = 0; i < sizeof(bundleA_gpios) / sizeof(bundleA_gpios[0]); i++)
    {
        uint32_t tmp = REG_READ(GPIO_FUNC0_OUT_SEL_CFG_REG+bundleA_gpios[i]*4);
        REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG+bundleA_gpios[i]*4,tmp | 1<<10);
    }

    while (1)
    {
        REG_WRITE(GPIO_ENABLE_W1TS_REG,oemask); // enable output
        for (int i = 0; i < 255; i++)
        {
            dedic_gpio_bundle_write(bundleA, 0xff, i);
        }

        REG_WRITE(GPIO_ENABLE_W1TC_REG,oemask); // disable output - out data always pulldown

        for (int i = 0; i < 255; i++)
        {
            dedic_gpio_bundle_write(bundleA, 0xff, i);
        }

        REG_WRITE(GPIO_ENABLE_W1TS_REG,oemask); // enable output
        
        for (int i = 0; i < 255; i++)
        {
            dedic_gpio_bundle_write(bundleA, 0xff, i);
        }
          
        vTaskDelay(1);
    }
}

void app_main(void)
{
    //logic_analyzer_ws_server();
    xTaskCreatePinnedToCore(dedic_task, "dedic", 4096, NULL, 5, NULL, 1);
    while (1)
    {
        vTaskDelay(10);
    }
}

Code: Select all

#include <stdio.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "driver/gpio.h"
#include "soc/gpio_reg.h"
#include "soc/io_mux_reg.h"
#include "soc/dport_access.h"

// 8 lines of data bus are assumed to be consecutive pads starting from DATA_BUS_LOWEST_PAD
// in this example lines: GPIO8 to GPIO15
// if you want to change that, change just starting pad number for DATA_BUS_LOWEST_PAD
// also take care not to overlap data-bus with pads required for external flash, PSRAM etc.  

#define DATA_BUS_LOWEST_PAD 8
#define SET_MASK (0x000000FF << DATA_BUS_LOWEST_PAD)
#define CLR_MASK (SET_MASK ^ 0xFFFFFFFF)

static __always_inline void  make_data_bus_in(void) { DPORT_REG_WRITE(GPIO_ENABLE_W1TC_REG, SET_MASK);}
static __always_inline void make_data_bus_out(void) { DPORT_REG_WRITE(GPIO_ENABLE_W1TS_REG, SET_MASK);}
static __always_inline void  write_db(uint8_t val) { DPORT_REG_WRITE(GPIO_OUT_REG, (_DPORT_REG_READ(GPIO_OUT_REG) & CLR_MASK) | (val << DATA_BUS_LOWEST_PAD));}
static __always_inline uint8_t read_db(void){ return (_DPORT_REG_READ(GPIO_IN_REG) >> DATA_BUS_LOWEST_PAD);}

void app_main(void)
{
//CONFIGURATION PART

   // unfortunately IO_MUX_GPIOx_REG are not positioned in memory map in ascending order
    // so there is no easy way to calculate their address, based on GPIO index (we would needed some remapping array) 
    // so user have to rename them manually if he changes DATA_BUS_LOWEST_PAD to some other value 
    // we set: MCU_SEL to 2 (it provides GPIO pad functionality),
    //         FUN_IE (this bit allows input from a pad to IO mux,
    //         FUN_WPD (pull down resistors to define data-bus state in the case no external peripheral write to it)

    DPORT_REG_WRITE(IO_MUX_GPIO8_REG, 0x00002280);
    DPORT_REG_WRITE(IO_MUX_GPIO9_REG, 0x00002280);
    DPORT_REG_WRITE(IO_MUX_GPIO10_REG, 0x00002280);
    DPORT_REG_WRITE(IO_MUX_GPIO11_REG, 0x00002280);
    DPORT_REG_WRITE(IO_MUX_GPIO12_REG, 0x00002280);
    DPORT_REG_WRITE(IO_MUX_GPIO13_REG, 0x00002280);
    DPORT_REG_WRITE(IO_MUX_GPIO14_REG, 0x00002280);
    DPORT_REG_WRITE(IO_MUX_GPIO15_REG, 0x00002280);

    //  GPIO_FUNCx_OUT_SEL_CFG_REG are consecutive in memory so we can use math to calc proper 
    //  register offset using GPIO index 
    //  we set forced OE (bit 10) and also set matrix function 0x100 (in bits 0 to 8) 

    DPORT_REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (DATA_BUS_LOWEST_PAD     ) * 4 ,  0x00000500);
    DPORT_REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (DATA_BUS_LOWEST_PAD + 1) * 4 ,  0x00000500);
    DPORT_REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (DATA_BUS_LOWEST_PAD + 2) * 4 ,  0x00000500);
    DPORT_REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (DATA_BUS_LOWEST_PAD + 3) * 4 ,  0x00000500);
    DPORT_REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (DATA_BUS_LOWEST_PAD + 4) * 4 ,  0x00000500);
    DPORT_REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (DATA_BUS_LOWEST_PAD + 5) * 4 ,  0x00000500);
    DPORT_REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (DATA_BUS_LOWEST_PAD + 6) * 4 ,  0x00000500);
    DPORT_REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (DATA_BUS_LOWEST_PAD + 7) * 4 ,  0x00000500);

// HERE IS THE USAGE PART:
// when you need to put byte(s)
    make_data_bus_out();
    write_db(0x00);
    write_db(0x01);
    ...

// when you need to read from some external peripheral       
    uint8_t value;
    make_data_bus_in();
    // trigger  OE on those external peripheral (for example some 8-bit latch or other MCU) to switch its output from tri-state and 
   // allows it on bus
   value = read_db();
   // use value
   // trigger another device     
   value = read_db();
   ...
}