Strange esp reset reason ( RTC_SW_SYS_RESET :Software reset digital core)
Posted: Mon Oct 02, 2023 8:42 am
Hello,
I'm using esp32 target and esp-idf v4.3
In my application I'm using `rtc_get_reset_reason()` to get the reset reason for each core and report it in my data.
In deployed devices in the field I get from time to time reset reasons 3 and 14 for core 0 and 1 respectively.
3, Software reset digital core
14 doesn't exist anywhere ?
I have never encountered these values while doing tests so I was wondering if you can help me identify what 3, Software reset digital core mean first ?
I found in technical manual the following
I'm using esp32 target and esp-idf v4.3
In my application I'm using `rtc_get_reset_reason()` to get the reset reason for each core and report it in my data.
Code: Select all
rtc_get_reset_reason(0);
rtc_get_reset_reason(1);
In deployed devices in the field I get from time to time reset reasons 3 and 14 for core 0 and 1 respectively.
3, Software reset digital core
14 doesn't exist anywhere ?
I have never encountered these values while doing tests so I was wondering if you can help me identify what 3, Software reset digital core mean first ?
Code: Select all
typedef enum {
NO_MEAN = 0,
POWERON_RESET = 1, /**<1, Vbat power on reset*/
RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/
DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core*/
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
EFUSE_RESET = 20, /**<20, efuse reset digital core*/
USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */
USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */
POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/
} RESET_REASON;