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uint8_t dma_links_init(bool printInfo, lldesc_t *ptrLink, uint32_t *dma_buf32){
	int32_t	total_bytes = DMA_JUNK_BUFFER_MAX_BYTES; // defined as 16384 bytes
	uint8_t i=0;

	do{
		total_bytes -= DMA_LINK_DATA_MAX_BYTES; // defined as 4092

		ptrLink->owner = 1;	// = DMA
		ptrLink->eof = (total_bytes<=0)? 1 : 0;
		ptrLink->sosf = 0;
		ptrLink->offset = 0;
		ptrLink->size = DMA_LINK_DATA_MAX_BYTES;
		ptrLink->length = (total_bytes>=0)? DMA_LINK_DATA_MAX_BYTES : (DMA_LINK_DATA_MAX_BYTES + total_bytes);
		ptrLink->buf = (const volatile uint8_t*) dma_buf32;
		ptrLink->empty = (uint32_t) ((total_bytes <= 0)? 0 : (ptrLink + 1));
		if(printInfo){
			printf("%02d. [ addr: %08lX ]	bytes: %d / %d, 	buf = %08lX,	next_addr = %08lX	EOF = %d\n",
				i,
				(uint32_t)ptrLink,
				ptrLink->length,
				ptrLink->size,
				(uint32_t)ptrLink->buf,
				(uint32_t)(ptrLink->empty),
				ptrLink->eof);
			fflush(0);
			}
		i++;
		dma_buf32 += (i*DMA_LINK_DATA_MAX_BYTES/4);
		ptrLink++;
		}while(total_bytes > 0);
	return i;
}

Code: Select all

    periph_module_enable(PERIPH_I2S0_MODULE);

	// Module Reset = TRM p.312 "In order to finish a reset operation, the corresponding bit should be set and then cleared by software."
	I2S0.conf.val |= (BIT_RX_RESET | BIT_RX_FIFO_RESET); // = 0b1 | 0b100
	I2S0.conf.val &= ~(BIT_RX_RESET | BIT_RX_FIFO_RESET);
	I2S0.lc_conf.val |= (BIT_DMA_FSM_IN_RESET | BIT_DMA_AHBM_FIFO_RESET | BIT_DMA_ABM_RESET); // = 0b1 | 0b100 | 0b1000
	I2S0.lc_conf.val &= ~(BIT_DMA_FSM_IN_RESET | BIT_DMA_AHBM_FIFO_RESET | BIT_DMA_ABM_RESET);

	I2S0.conf.rx_slave_mod = 1;
	I2S0.conf.rx_right_first = 0;
	I2S0.conf.rx_msb_right = 0;
	I2S0.conf.rx_msb_shift = 0; 
	I2S0.conf.rx_mono = 0;
	I2S0.conf.rx_short_sync = 0;

	I2S0.conf2.lcd_en = 1;
	I2S0.conf2.camera_en = 1;

	I2S0.clkm_conf.clkm_div_a = 0;
	I2S0.clkm_conf.clkm_div_b = 0;
	I2S0.clkm_conf.clkm_div_num = 2;

	I2S0.fifo_conf.dscr_en = 1;	
	I2S0.fifo_conf.rx_fifo_mod = SM_0A00_0B00;
	I2S0.fifo_conf.rx_fifo_mod_force_en = 1;
	I2S0.fifo_conf.rx_data_num = 0b111111;

	I2S0.conf_chan.rx_chan_mod = 1;

	I2S0.sample_rate_conf.rx_bits_mod = 0;
	I2S0.timing.val = 0;
    	I2S0.timing.rx_dsync_sw = 1;

	I2S0.int_ena.val = 0;
	I2S0.int_clr.val = I2S0.int_raw.val;

	I2S0.in_link.addr = ((uint32_t)(&dma_links)) & 0b11111111111111111111; // 20-bit length. just to look fancy :)
	I2S0.rx_eof_num = DMA_JUNK_BUFFER_MAX_BYTES; // = 16834

	esp_intr_enable(hCam->hIntr);

Code: Select all

void IRAM_ATTR I2S_Vsync_ISR(){
	I2S0.int_clr.in_suc_eof = 1;
	I2S0.int_ena.in_suc_eof = 1;

// I2S0.int_clr.in_done = 1; // for testing and debugging purposes
// I2S0.int_ena.in_done = 1; // for testing and debugging purposes

	// here's an optional call to set all the link descriptors any other call (in case the content DOES CHANGE; still to be examined) 
	dma_links_init(0, (lldesc_t*)&dma_links, (uint32_t*)&dma_junk_buf);

	// start off DMA
	I2S0.in_link.start = 1;
	I2S0.conf.rx_start = 1;

	gpio_intr_disable(hCam->pin_vsync); // self-disabling
}

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void IRAM_ATTR I2S_ISR(){
	BaseType_t Woken = 0;
	uint32_t msg = MSG_DMA_IN_SUC_EOF;

	// NOTE: the int flag is cleared only on successful QueueSend() so that in case of failure (queue is full) ESP32 re-enters the handler again:
	if(xQueueSendFromISR(hCam->hQueue, &msg, &Woken) == pdTRUE) I2S0.int_clr.in_suc_eof = 1;
	else{
		// perform some termination stuff
		// ..
		ESP_DRAM_LOGE("in_suc_eof", "ERROR: xQueueSendFromISR() failed\n"); // just for debugging purposes
		}
	if(Woken) portYIELD_FROM_ISR();
}