I2C Clock Flush
Posted: Wed Sep 06, 2023 6:01 am
When using I2C, sometimes downstream devices are in the middle of a transaction when the ESP resets. This causes them to hold the SDA line low, while the SCL line is high, which apparently confuses the ESP I2C stack?
Is there a proper way to "flush" I2C transactions by toggling the clock line several times to get the bus back in a functional state?
Is there a proper way to "flush" I2C transactions by toggling the clock line several times to get the bus back in a functional state?