ESP32 Forum

ESP32 Official Forum
http://esp32.io/

Can't change field values in I2C_CTR_REG on esp32s3

http://esp32.io/viewtopic.php?f=13&t=33345

Page 1 of 1

Can't change field values in I2C_CTR_REG on esp32s3

Posted: Tue Apr 25, 2023 3:28 pm
by mike7_hw
Hello,

I've been trying to manually configure ESP32S3 registers on my custom PCB in order to set-up an I2C communication. The purpose is to get hands-on experience in writing device drivers and working with register fields/addresses.

I'm using ESP-IDF v5.1 with VS code.

In esp32-s3 Technical Reference Manual, this can be done by working inside I2C_CTR_REG register.

I selected I2C0 register whose base address is 0x60013000.

I've encountered two issues while trying to achieve this.

1st (Bonus) - The IO_MUX_n_REGISTER reset state is different from what is written in the TRM.
Screenshot 2023-04-25 at 16-47-18 esp32-s3_technical_reference_manual_en.pdf.png
IO_MUX_n_REG
Screenshot 2023-04-25 at 16-47-18 esp32-s3_technical_reference_manual_en.pdf.png (24.05 KiB) Viewed 1060 times
From the above picture, the reset state of the register field should be 0x00000800 (bit 11 set). However, the value I read is 0x00000A02 (bit 1, 9 and 11 set).
Since I can write into this register, I will just clear the unwanted bits before setting the register field to my desired value. Still, if someone as any idea why there is a difference when I only am reading the register.


2nd - I can't write into I2C_CTR_REG.

As far as I understand it, the register can be accessed for reading and writing. However, the field value doesn't change. The field seems "locked". Is there an additional step to perform before trying to configure this register?
Screenshot 2023-04-25 at 17-00-04 esp32-s3_technical_reference_manual_en.pdf.png
I2C_CTR_REG
Screenshot 2023-04-25 at 17-00-04 esp32-s3_technical_reference_manual_en.pdf.png (149.46 KiB) Viewed 1060 times
Here is a code sample:

Code: Select all

int set_I2C_in_master_mode()
{
    volatile uint32_t *address_of_I2C_control_register = (volatile uint32_t *) (I2C_CTR_REG);
    printf("I2C Control Reg content before setting bits: 0x%08lX\n", *address_of_I2C_control_register);

    *address_of_I2C_control_register = (*address_of_I2C_control_register) | (1 << I2C_MS_MODE_FIELD);
    
    printf("I2C Control Reg content after setting bits: 0x%08lX\n", *address_of_I2C_control_register);

    return(0);
}

int app_main()
{
    set_I2C_in_master_mode();
    return(0);
}
And this here is the terminal output (line 71 and 72 show the register content before and after trying to write):
Code: [Select all] [Expand/Collapse]
  1. --- idf_monitor on /dev/ttyACM0 115200 ---
  2. --- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H ---
  3. I (99) boot:  2 factory          factory app      00 00 0ESP-ROM:esp32s3-20210327
  4. Build:Mar 27 2021
  5. rst:0x15 (USB_UART_CHIP_RESET),boot:0x2b (SPI_FAST_FLASH_BOOT)
  6. Saved PC:0x403783ce
  7. 0x403783ce: esp_cpu_wait_for_intr at /home/user/esp/esp-idf/components/esp_hw_support/cpu.c:121
  8.  
  9. SPIWP:0xee
  10. mode:DIO, clock div:1
  11. load:0x3fce3818,len:0x16f4
  12. load:0x403c9700,len:0x4
  13. load:0x403c9704,len:0xc00
  14. load:0x403cc700,len:0x2eb0
  15. SHA-256 comparison failed:
  16. Calculated: a09bd1ec3e34ce03e0714dec31f74919e5988cd476f954f99420bebf61b3505c
  17. Expected: ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
  18. Attempting to boot anyway...
  19. entry 0x403c9908
  20. I (45) boot: ESP-IDF v5.1-dev-4557-gf404fe96b1 2nd stage bootloader
  21. I (45) boot: compile time Apr 25 2023 14:38:20
  22. I (46) boot: Multicore bootloader
  23. I (50) boot: chip revision: v0.1
  24. I (54) boot.esp32s3: Boot SPI Speed : 80MHz
  25. I (59) boot.esp32s3: SPI Mode       : DIO
  26. I (63) boot.esp32s3: SPI Flash Size : 8MB
  27. I (68) boot: Enabling RNG early entropy source...
  28. I (73) boot: Partition Table:
  29. I (77) boot: ## Label            Usage          Type ST Offset   Length
  30. I (84) boot:  0 nvs              WiFi data        01 02 00009000 00006000
  31. I (92) boot:  1 phy_init         RF data          01 01 0000f000 00001000
  32. I (99) boot:  2 factory          factory app      00 00 00010000 00100000
  33. I (107) boot: End of partition table
  34. I (111) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=09cd8h ( 40152) map
  35. I (124) esp_image: segment 1: paddr=00019d00 vaddr=3fc91300 size=027f8h ( 10232) load
  36. I (129) esp_image: segment 2: paddr=0001c500 vaddr=40374000 size=03b18h ( 15128) load
  37. I (139) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=17780h ( 96128) map
  38. I (156) esp_image: segment 4: paddr=000377a8 vaddr=40377b18 size=097d4h ( 38868) load
  39. I (167) boot: Loaded app from partition at offset 0x10000
  40. I (168) boot: Disabling RNG early entropy source...
  41. I (179) cpu_start: Multicore app
  42. I (179) cpu_start: Pro cpu up.
  43. I (179) cpu_start: Starting app cpu, entry point is 0x4037523c
  44. 0x4037523c: call_start_cpu1 at /home/user/esp/esp-idf/components/esp_system/port/cpu_start.c:159
  45.  
  46. I (0) cpu_start: App cpu up.
  47. I (198) cpu_start: Pro cpu start user code
  48. I (198) cpu_start: cpu freq: 160000000 Hz
  49. I (198) cpu_start: Application information:
  50. I (201) cpu_start: Project name:     template-app
  51. I (206) cpu_start: App version:      1
  52. I (210) cpu_start: Compile time:     Apr 25 2023 14:38:16
  53. I (217) cpu_start: ELF file SHA256:  d19cfdc68d829505...
  54. I (223) cpu_start: ESP-IDF:          v5.1-dev-4557-gf404fe96b1
  55. I (229) cpu_start: Min chip rev:     v0.0
  56. I (234) cpu_start: Max chip rev:     v0.99
  57. I (239) cpu_start: Chip rev:         v0.1
  58. I (243) heap_init: Initializing. RAM available for dynamic allocation:
  59. I (251) heap_init: At 3FC94340 len 000553D0 (340 KiB): DRAM
  60. I (257) heap_init: At 3FCE9710 len 00005724 (21 KiB): STACK/DRAM
  61. I (263) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
  62. I (270) heap_init: At 600FE010 len 00001FF0 (7 KiB): RTCRAM
  63. I (277) spi_flash: detected chip: generic
  64. I (281) spi_flash: flash io: dio
  65. I (285) sleep: Configure to isolate all GPIO pins in sleep state
  66. I (291) sleep: Enable automatic switching of GPIO sleep configuration
  67. I (299) app_start: Starting scheduler on CPU0
  68. I (303) app_start: Starting scheduler on CPU1
  69. I (303) main_task: Started on CPU0
  70. I (313) main_task: Calling app_main()
  71. I2C Control Reg content before setting bits: 0x0000020B
  72. I2C Control Reg content after setting bits: 0x0000020B
  73. I (323) main_task: Returned from app_main()
GeSHi © Codebox Plus Extension
Thanks in advance for those of you that are taking some time to help me sort this out!

Mike

Re: Can't change field values in I2C_CTR_REG on esp32s3

Posted: Wed Apr 26, 2023 1:07 am
by ESP_Sprite
You need to enable the peripheral first. See here for how to do that.

Re: Can't change field values in I2C_CTR_REG on esp32s3

Posted: Fri Apr 28, 2023 2:04 pm
by mike7_hw
Hello,

Thanks for your feedback.
In the meantime I had already found an answer:

1. SYSTEM_I2C_EXT0_RST field in SYSTEM_PERIP_RST_EN0_REG register had to be cleared to enable the I2CEXT0 peripheral
2. SYSTEM_I2C_EXT0_CLK_EN field in SYSTEM_PERIP_CLK_EN0_REG register hat to be set to enable the clock to I2CEXT0 peripheral.

Best,
All times are UTC
Page 1 of 1
Powered by phpBB® Forum Software © phpBB Limited
https://www.phpbb.com/