ESP32 Forum

Good afternoon,

I would like to set the bit IO_MUX_FILTER_EN of the IO_MUX_42_REG register but I don't know how to do it ...
How can I write the corresponding Software code line please ??

Something like IO_MUX_42_REG.IO_MUX_FILTER_EN = 1 ???

I have not understood how to access the bits of the registers.

Best regards,

Thomas TRUILHE

The same thing, I would like to set the GPIO_PIN42_SYNC1_BYPASS and GPIO_PIN42_SYNC2_BYPASS bit of the GPIO_PIN42_REG register.

This because I am following the paragraph "Peripheral Input via GPIO Matrix" => Functional Description
of the ESP32-S3 reference manual. I would like to set the Pin 42 to the SPI3 peripheral.

1) Configure register GPIO_FUNCy_IN_SEL_CFG_REG corresponding to peripheral signal Y in GPIO matrix:

• Set GPIO_SIGy_IN_SEL to enable peripheral signal input via GPIO matrix.
• Set GPIO_FUNCy_IN_SEL to the desired GPIO pin.

2) Optionally enable the filter for pin input signals by setting the register IO_MUX_FILTER_EN. Only the signals
with a valid width of more than two APB clock cycles can be sampled.

3) Synchronize GPIO input. To do so, please set GPIO_PINx_REG corresponding to GPIO pin X as follows:
• Set GPIO_PINx_SYNC1_BYPASS to enable input signal synchronized on rising edge or on falling edge
in the first clock.
• Set GPIO_PINx_SYNC2_BYPASS to enable input signal synchronized on rising edge or on falling edge
in the second clock.

4) Configure IO MUX register to enable pin input. For this end, please set IO_MUX_X_REG corresponding to
GPIO pin x as follows:
• Set IO_MUX_FUN_IE to enable input2

• Set or clear IO_MUX_FUN_WPU and IO_MUX_FUN_WPD, as desired, to enable or disable pull-up
and pull-down resistors.

Best regards,

If neither the SPI nor the GPIO driver support what you want, you can go about it like this:
and
Both "SYNCx_BYPASS" fields seem to be two-bit values, so check which value (0...3) you need to set.