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bdc_motor doesn't work with psram enabled

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bdc_motor doesn't work with psram enabled

Posted: Tue Feb 28, 2023 12:31 am
by mcmillanje
Wondering if anyone can help me figure this out. Here's my sample code. I've broken it down to as simple as I can to eliminate potential causes:
Code: [Select all] [Expand/Collapse]
  1. #include <stdio.h>
  2.  
  3. #include "freertos/FreeRTOS.h"
  4. #include "freertos/task.h"
  5. #include "freertos/queue.h"
  6. #include "driver/gpio.h"
  7. #include "esp_log.h"
  8. #include "iot_button.h"
  9. #include "esp_timer.h"
  10. #include "bdc_motor.h"
  11. #include <string.h>
  12.  
  13. #define BDC_MCPWM_TIMER_RESOLUTION_HZ 10000000 // 10MHz, 1 tick = 0.1us
  14. #define BDC_MCPWM_FREQ_HZ             25000    // 25KHz PWM
  15. #define BDC_MCPWM_DUTY_TICK_MAX       (BDC_MCPWM_TIMER_RESOLUTION_HZ / BDC_MCPWM_FREQ_HZ) // maximum value we can set for the duty cycle, in ticks
  16. #define BDC_MCPWM_GPIO_A              12 // forward
  17. #define BDC_MCPWM_GPIO_B              16 // backward
  18.  
  19. #define MOTORSPEED 200
  20.  
  21. static const char *TAG = "example";
  22.  
  23. void app_main(void)
  24. {
  25.     ESP_LOGI(TAG, "Create DC motor");
  26.     bdc_motor_config_t motor_config = {
  27.         .pwm_freq_hz = BDC_MCPWM_FREQ_HZ,
  28.         .pwma_gpio_num = BDC_MCPWM_GPIO_A,
  29.         .pwmb_gpio_num = BDC_MCPWM_GPIO_B,
  30.     };        
  31.     bdc_motor_mcpwm_config_t mcpwm_config = {
  32.         .group_id = 0,
  33.         .resolution_hz = BDC_MCPWM_TIMER_RESOLUTION_HZ,
  34.     };    
  35.     bdc_motor_handle_t motor = NULL;
  36.     ESP_ERROR_CHECK(bdc_motor_new_mcpwm_device(&motor_config, &mcpwm_config, &motor));
  37.  
  38.     ESP_LOGI(TAG, "Enable motor");
  39.     ESP_ERROR_CHECK(bdc_motor_enable(motor));
  40.     bdc_motor_set_speed(motor,MOTORSPEED); // max 400
  41.  
  42.     while(1) {
  43.         ESP_ERROR_CHECK(bdc_motor_forward(motor));
  44.         vTaskDelay(5000/ portTICK_PERIOD_MS);
  45.         ESP_ERROR_CHECK(bdc_motor_reverse(motor));
  46.         vTaskDelay(5000/ portTICK_PERIOD_MS);
  47.     }
  48.  
  49. }
GeSHi © Codebox Plus Extension
This works just fine until I enable PSRAM in menuconfig (the hardware is aithinker esp32-cam)

Once I enable PSRAM I get this output:

Code: Select all

I (27) boot: ESP-IDF v5.0 2nd stage bootloader
I (27) boot: compile time 11:28:30
I (27) boot: chip revision: v3.0
I (30) boot_comm: chip revision: 3, min. bootloader chip revision: 0
I (37) boot.esp32: SPI Speed      : 40MHz
I (42) boot.esp32: SPI Mode       : DIO
I (46) boot.esp32: SPI Flash Size : 2MB
I (51) boot: Enabling RNG early entropy source...
I (56) boot: Partition Table:
I (60) boot: ## Label            Usage          Type ST Offset   Length
I (67) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (75) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (82) boot:  2 factory          factory app      00 00 00010000 00100000
I (90) boot: End of partition table
I (94) boot_comm: chip revision: 3, min. application chip revision: 0
I (101) esp_image: segment 0: paddr=00010020 vaddr=3f400020 size=0e48ch ( 58508) map
I (131) esp_image: segment 1: paddr=0001e4b4 vaddr=3ffb0000 size=01b64h (  7012) load
I (134) esp_image: segment 2: paddr=00020020 vaddr=400d0020 size=1f420h (128032) map
I (183) esp_image: segment 3: paddr=0003f448 vaddr=3ffb1b64 size=00ed4h (  3796) load
I (184) esp_image: segment 4: paddr=00040324 vaddr=40080000 size=10054h ( 65620) load
I (215) esp_image: segment 5: paddr=00050380 vaddr=50000000 size=00010h (    16) load
I (224) boot: Loaded app from partition at offset 0x10000
I (224) boot: Disabling RNG early entropy source...
I (236) quad_psram: This chip is ESP32-D0WD
I (238) esp_psram: Found 8MB PSRAM device
I (238) esp_psram: Speed: 40MHz
I (240) esp_psram: PSRAM initialized, cache is in low/high (2-core) mode.
W (247) esp_psram: Virtual address not enough for PSRAM, map as much as we can. 4MB is mapped
I (256) cpu_start: Pro cpu up.
I (260) cpu_start: Starting app cpu, entry point is 0x400812d8
0x400812d8: call_start_cpu1 at C:/Users/mcmil/esp/esp-idf/components/esp_system/port/cpu_start.c:142

I (253) cpu_start: App cpu up.
I (1172) esp_psram: SPI SRAM memory test OK
I (1180) cpu_start: Pro cpu start user code
I (1180) cpu_start: cpu freq: 160000000 Hz
I (1180) cpu_start: Application information:
I (1184) cpu_start: Project name:     motor_test
I (1189) cpu_start: App version:      1
I (1193) cpu_start: Compile time:     Feb 27 2023 16:25:40
I (1200) cpu_start: ELF file SHA256:  07d7022c92f125ad...
I (1206) cpu_start: ESP-IDF:          v5.0
I (1211) heap_init: Initializing. RAM available for dynamic allocation:
I (1218) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (1224) heap_init: At 3FFB3428 len 0002CBD8 (178 KiB): DRAM
I (1230) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (1237) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (1243) heap_init: At 40090054 len 0000FFAC (63 KiB): IRAM
I (1250) esp_psram: Adding pool of 4096K of PSRAM memory to heap allocator
I (1258) spi_flash: detected chip: generic
I (1262) spi_flash: flash io: dio
W (1266) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
I (1280) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
I (1290) esp_psram: Reserving pool of 32K of internal memory for DMA/internal allocations
I (1300) example: Create DC motor
I (1300) gpio: GPIO[12]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0 
I (1310) gpio: GPIO[16]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
Guru Meditation Error: Core  0 panic'ed (LoadProhibited). Exception was unhandled.

Core  0 register dump:
PC      : 0x400dbdd9  PS      : 0x00060c30  A0      : 0x800da756  A1      : 0x3ffb5e50
0x400dbdd9: mcpwm_generator_set_actions_on_timer_event at C:/Users/mcmil/esp/esp-idf/components/driver/mcpwm/mcpwm_gen.c:155 (discriminator 2)

A2      : 0x3f800994  A3      : 0x00000000  A4      : 0x00000000  A5      : 0xffffffff
A6      : 0x00000000  A7      : 0x3f40ae7c  A8      : 0x800dbaf6  A9      : 0x3ffb5e60
A10     : 0x3ff44570  A11     : 0x00000021  A12     : 0x0ffd114c  A13     : 0x00000000  
A14     : 0x00000000  A15     : 0x00010000  SAR     : 0x00000010  EXCCAUSE: 0x0000001c
EXCVADDR: 0x00000003  LBEG    : 0x40087ea1  LEND    : 0x40087eb1  LCOUNT  : 0xfffffffe  
0x40087ea1: strlen at /builds/idf/crosstool-NG/.build/HOST-x86_64-w64-mingw32/xtensa-esp32-elf/src/newlib/newlib/libc/machine/xtensa/strlen.S:84

0x40087eb1: strlen at /builds/idf/crosstool-NG/.build/HOST-x86_64-w64-mingw32/xtensa-esp32-elf/src/newlib/newlib/libc/machine/xtensa/strlen.S:96



Backtrace: 0x400dbdd6:0x3ffb5e50 0x400da753:0x3ffb5ee0 0x400da09d:0x3ffb5fa0 0x400ef248:0x3ffb5fe0 0x4008c4b9:0x3ffb6010
0x400dbdd6: mcpwm_generator_set_actions_on_timer_event at C:/Users/mcmil/esp/esp-idf/components/driver/mcpwm/mcpwm_gen.c:154 (discriminator 2)

0x400da753: bdc_motor_new_mcpwm_device at C:/Users/mcmil/motor_test/managed_components/espressif__bdc_motor/src/bdc_motor_mcpwm_impl.c:138 (discriminator 2)

0x400da09d: app_main at C:/Users/mcmil/motor_test/main/test.c:36

0x400ef248: main_task at C:/Users/mcmil/esp/esp-idf/components/freertos/FreeRTOS-Kernel/portable/port_common.c:131 (discriminator 2)

0x4008c4b9: vPortTaskWrapper at C:/Users/mcmil/esp/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c:151

Re: bdc_motor doesn't work with psram enabled

Posted: Tue Feb 28, 2023 2:13 am
by username
I think IO16 is used for PSAM.

Re: bdc_motor doesn't work with psram enabled

Posted: Tue Feb 28, 2023 2:18 am
by mcmillanje
I actually figured it out. I had to enable "Place MCPWM ISR function into IRAM" and "Place MCPWM control functions into IRAM" in menuconfig.

Thanks for the tip about io16 though! I was having weird behavior where it spun the motor on boot as well so maybe that's why. Thanks!
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