ESP32 Forum

Hi!

I need to store a very few of data during deepsleep and use minimal energy consumption as possible. I really don't like to use nvs storage for this, because it may exhaust erasing capacity of the flash chip.

My strategy is to power down all rtc domains during deepsleep and to use some of RTC_CNTL_STOREx_REGs to store my 2 words of data.

But from sources i see that all there RTC_CNTL_STOREx_REGs are occupied by data for the bootloader. I supposed to use only RTC_CNTL_STORE6_REG and RTC_CNTL_STORE7_REG for my data, because I am not going to use the deep sleep stub. But it looks like these registers are not under my control anyway: RTC_CNTL_STORE6_REG = 0 , RTC_CNTL_STORE7_REG = <some int> after every boot up.

After deep sleep I have 2 consequent resets on boot:

rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)

But any of these is not the System reset and then RTC registers shouldn't be reset. Probably I am mistaking...

My sources is release/2.1.

Please, show me the way))

Thanks in advance!!

Is it because of ECO 3.1 Due to the cache MMU bug, a spurious watchdog reset occurs when ESP32 is powered up or wakes up from Deep-
sleep.

WiFive wrote:Is it because of ECO 3.1 Due to the cache MMU bug, a spurious watchdog reset occurs when ESP32 is powered up or wakes up from Deep-
sleep.

Sorry, but what is ESO 3.1?

And as far as I remember, it was pointed in documentation, that spurious wd resets are coming due to late power up for flash chip that blocks loading of the code and wd is resetting system after some period. Or, am I wong?

http://espressif.com/sites/default/file ... p32_en.pdf

There are different types of wdt reset issue. With rev0 you have to use default wake stub to prevent reset.

WiFive wrote:http://espressif.com/sites/default/file ... p32_en.pdf

There are different types of wdt reset issue. With rev0 you have to use default wake stub to prevent reset.

Yes, WiFive, I know, but I am trying to use the hibernate mode where all rtc domains are down. But the wake stub requires to be in rtc memory.

I've added some info to the main post regarding different resets types.

WiFive wrote:http://espressif.com/sites/default/file ... p32_en.pdf

There are different types of wdt reset issue. With rev0 you have to use default wake stub to prevent reset.

Ahh, I see what the ECO 3.1 is!! Thanks, WiFive))

So, do you think there is no luck to use my approcah?

https://github.com/espressif/esp-idf/bl ... des.c#L157

That function will always set RTC_CNTL_STORE6_REG and RTC_CNTL_STORE7_REG

If you bypass that they should not get overwritten and I think they may even survive the wdt reset unlike ram

WiFive wrote:https://github.com/espressif/esp-idf/bl ... des.c#L157

That function will always set RTC_CNTL_STORE6_REG and RTC_CNTL_STORE7_REG

If you bypass that they should not get overwritten and I think they may even survive the wdt reset unlike ram

Yes, i see, you are right! I'll try.

WiFive, It works!

But in my case of using release/v2.1 the code is here: https://github.com/espressif/esp-idf/bl ... eep.c#L130

I've just commented it and registers are not reset. Many thanks!

If you bypass that they should not get overwritten and I think they may even survive the wdt reset unlike ram

That is actually the other way around: RTC registers will by reset if either TG or RTC watchdog triggers SYS reset, and memories are never reset.