ESP32 Forum

Posted: **Tue Sep 19, 2017 8:01 am**

Hi,
As the esp32_technical_reference_manual_en.pdf mentioned that MCLK could output via GPIO0,I try below code:

         //output clock for I2S0 to CLK_OUT1
	//pdf page 67
	//(*((int*)PIN_CTRL)) = (*((int*)PIN_CTRL))&0xFFFFFFF0;
	reg_val = REG_READ(PIN_CTRL);
	ESP_LOGI(TAG, "PIN_CTRL before:%x", reg_val);
	REG_WRITE(PIN_CTRL, 0xFFFFFFF0);
	reg_val = REG_READ(PIN_CTRL);
	ESP_LOGI(TAG, "PIN_CTRL after:%x", reg_val);
	//(*((int*)PIN_CTRL)) = 0xFFFFFFF0;
	PIN_FUNC_SELECT(GPIO_PIN_REG_0, 1); //GPIO0 as CLK_OUT1

unfortunately,the GPIO0 output a noise CLK.like this:

log is:
I (1372) I2S: DMA Malloc info, datalen=blocksize=240, dma_buf_count=6
I (1382) I2S: Req RATE: 44100, real rate: 44642.000, BITS: 16, CLKM: 14, BCK: 8, MCLK: 11289966.924, SCLK: 1428544.000000, diva: 64, divb: 11
D (1392) I2S: data: out 163, in: -1, ws: 25, bck: 23
I (1402) Huan: PIN_CTRL before:3ff
I (1402) Huan: PIN_CTRL after:7ff0
I (1412) wifi: n:6 0, o:1 0, ap:255 255, sta:6 0, prof:1
I (1412) I2S: Req RATE: 22050, real rate: 22321.000, BITS: 16, CLKM: 28, BCK: 8, MCLK: 5644983.462, SCLK: 714272.000000, diva: 64, divb: 22
I (1432) I2S: Req RATE: 44100, real rate: 44642.000, BITS: 16, CLKM: 14, BCK: 8, MCLK: 11289966.924, SCLK: 1428544.000000, diva: 64, divb: 11
My question is :How enable I2S0 MCLK ouput via GPIO0?
Any help will be appreciate.

Posted: **Tue Sep 19, 2017 8:54 am**

Are you sure the noise is in the output on the GPIO and not your measuring system? You can easily get stuff like this if your probes bandwith is too low, you use pigtails off the probe pin, or your ground isn't in the right position.

Posted: **Wed Sep 20, 2017 2:21 am**

ESP_Sprite wrote:Are you sure the noise is in the output on the GPIO and not your measuring system? You can easily get stuff like this if your probes bandwith is too low, you use pigtails off the probe pin, or your ground isn't in the right position.

Hi ESP_Sprite,
I have measure the WS and BCLK at the same time, and the signal is quite good.So there is no problem with measuring system. I guess I have not configure the MCLK output properly.Please check my code below:

Code: Select all

//output clock for I2S0 to CLK_OUT1
   //pdf page 67
   //(*((int*)PIN_CTRL)) = (*((int*)PIN_CTRL))&0xFFFFFFF0;
   reg_val = REG_READ(PIN_CTRL);
   ESP_LOGI(TAG, "PIN_CTRL before:%x", reg_val);
   REG_WRITE(PIN_CTRL, 0xFFFFFFF0);
   reg_val = REG_READ(PIN_CTRL);
   ESP_LOGI(TAG, "PIN_CTRL after:%x", reg_val);
   //(*((int*)PIN_CTRL)) = 0xFFFFFFF0;
   PIN_FUNC_SELECT(GPIO_PIN_REG_0, 1); //GPIO0 as CLK_OUT1

any sample code?Thanks.

Posted: **Wed Sep 20, 2017 2:27 am**

ESP_Sprite wrote:Are you sure the noise is in the output on the GPIO and not your measuring system? You can easily get stuff like this if your probes bandwith is too low, you use pigtails off the probe pin, or your ground isn't in the right position.

I have measured the WS and BCLK and signal is good,except the MCLK.Please help tcheck my code:

Code: Select all

//output clock for I2S0 to CLK_OUT1
   //pdf page 67
   //(*((int*)PIN_CTRL)) = (*((int*)PIN_CTRL))&0xFFFFFFF0;
   reg_val = REG_READ(PIN_CTRL);
   ESP_LOGI(TAG, "PIN_CTRL before:%x", reg_val);
   REG_WRITE(PIN_CTRL, 0xFFFFFFF0);
   reg_val = REG_READ(PIN_CTRL);
   ESP_LOGI(TAG, "PIN_CTRL after:%x", reg_val);
   //(*((int*)PIN_CTRL)) = 0xFFFFFFF0;
   PIN_FUNC_SELECT(GPIO_PIN_REG_0, 1); //GPIO0 as CLK_OUT1

any sample code will be great.Thanks.

Posted: **Wed Sep 20, 2017 3:27 am**

Sure, but WS and BCLK are an order of magnitude slower than the MCLK signal. Can you show me these signals on the same scope setup? I'm still not sure your noise comes fromt he ESP32 and not your setup; it looks distinctly analog and rlc-based to me.

Posted: **Mon Jul 16, 2018 6:42 am**

fanday wrote:
ESP_Sprite wrote:Are you sure the noise is in the output on the GPIO and not your measuring system? You can easily get stuff like this if your probes bandwith is too low, you use pigtails off the probe pin, or your ground isn't in the right position.
I have measured the WS and BCLK and signal is good,except the MCLK.Please help tcheck my code:
Code: Select all
//output clock for I2S0 to CLK_OUT1
   //pdf page 67
   //(*((int*)PIN_CTRL)) = (*((int*)PIN_CTRL))&0xFFFFFFF0;
   reg_val = REG_READ(PIN_CTRL);
   ESP_LOGI(TAG, "PIN_CTRL before:%x", reg_val);
   REG_WRITE(PIN_CTRL, 0xFFFFFFF0);
   reg_val = REG_READ(PIN_CTRL);
   ESP_LOGI(TAG, "PIN_CTRL after:%x", reg_val);
   //(*((int*)PIN_CTRL)) = 0xFFFFFFF0;
   PIN_FUNC_SELECT(GPIO_PIN_REG_0, 1); //GPIO0 as CLK_OUT1
   
any sample code will be great.Thanks.

PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1);
REG_WRITE(PIN_CTRL, 0);

Posted: **Tue Oct 02, 2018 6:12 pm**

Hi,

Im trying to use i2s with sgtl5000 and stuck with MCLK generation.
Also my board don't have GPIO0 pin as it used as boot pin as button.
Kindly tell how can I generate 385*Fs(385*44100=16978500) or 256*Fs or 512*Fs via CLK_OUT3.
using below 2 functions but don't know how to divide the clock also please tell the clk_out3 source.
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_CLK_OUT3);
REG_WRITE(PIN_CTRL,0xFFFFF0F0);

Posted: **Mon Dec 10, 2018 11:20 pm**

npashine wrote: ↑
Tue Oct 02, 2018 6:12 pm
Hi,

Im trying to use i2s with sgtl5000 and stuck with MCLK generation.
Also my board don't have GPIO0 pin as it used as boot pin as button.
Kindly tell how can I generate 385*Fs(385*44100=16978500) or 256*Fs or 512*Fs via CLK_OUT3.
using below 2 functions but don't know how to divide the clock also please tell the clk_out3 source.
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_CLK_OUT3);
REG_WRITE(PIN_CTRL,0xFFFFF0F0);

Hey
Have you succeed to set the mclk to 512fs?

Posted: **Wed Dec 12, 2018 3:15 am**

Hi,
Just as Janet2018 suggested, I2S0 MCLK can output from IO0 , but note IO0 should not be connected to a capacitor.

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