esp32s3 enabling ext1 into deepsleep in esp-idf v4.4.1 environment will trigger a power-on reset

[Zakiu-C]

log as follows:
ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fcd0108,len:0x1714
load:0x403b6000,len:0xb7c
load:0x403ba000,len:0x3094
entry 0x403b6248
I (24) boot: ESP-IDF v4.4.1-dirty 2nd stage bootloader
I (25) boot: compile time 10:52:31
I (25) boot: chip revision: 0
I (27) boot.esp32s3: Boot SPI Speed : 80MHz
I (32) boot.esp32s3: SPI Mode : DIO
I (36) boot.esp32s3: SPI Flash Size : 2MB
I (41) boot: Enabling RNG early entropy source...
I (47) boot: Partition Table:
I (50) boot: ## Label Usage Type ST Offset Length
I (57) boot: 0 nvs WiFi data 01 02 00009000 00006000I (65) boot: 1 phy_init RF data 01 01 0000f000 00001000I (72) boot: 2 factory factory app 00 00 00010000 00100000I (80) boot: End of partition table
I (84) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=07f50h (
32592) map
I (98) esp_image: segment 1: paddr=00017f78 vaddr=3fc91e60 size=02774h (
10100) load
I (103) esp_image: segment 2: paddr=0001a6f4 vaddr=40374000 size=05924h ( 22820) load
I (114) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=1778ch ( 96140) map
I (135) esp_image: segment 4: paddr=000377b4 vaddr=40379924 size=08530h ( 34096) load
I (143) esp_image: segment 5: paddr=0003fcec vaddr=50000000 size=00010h ( 16) load
I (143) esp_image: segment 6: paddr=0003fd04 vaddr=600fe000 size=00028h ( 40) load
I (155) boot: Loaded app from partition at offset 0x10000
I (155) boot: Disabling RNG early entropy source...
I (172) cpu_start: Pro cpu up.
I (172) cpu_start: Starting app cpu, entry point is 0x403751e8
0x403751e8: call_start_cpu1 at H:/ESP32/Espressif/frameworks/esp-idf-v4.4.1/esp-idf-v4.4.1/components/esp_system/port/cpu_start.c:160

I (0) cpu_start: App cpu up.
I (186) cpu_start: Pro cpu start user code
I (186) cpu_start: cpu freq: 160000000
I (186) cpu_start: Application information:
I (189) cpu_start: Project name: deep_sleep
I (194) cpu_start: App version: 1
I (199) cpu_start: Compile time: Oct 19 2022 10:51:47
I (205) cpu_start: ELF file SHA256: d221e5cbd6a9a6da...
I (211) cpu_start: ESP-IDF: v4.4.1-dirty
I (216) heap_init: Initializing. RAM available for dynamic allocation:
I (223) heap_init: At 3FC94FD8 len 0004B028 (300 KiB): D/IRAM
I (230) heap_init: At 3FCE0000 len 0000EE34 (59 KiB): STACK/DRAM
I (236) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
I (243) heap_init: At 600FE028 len 00001FC8 (7 KiB): RTCRAM
I (249) spi_flash: detected chip: generic
I (254) spi_flash: flash io: dio
W (257) spi_flash: Detected size(8192k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
I (271) sleep: Configure to isolate all GPIO pins in sleep state
I (278) sleep: Enable automatic switching of GPIO sleep configuration
I (285) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
core 0: 01 core 1: 01
Not a deep sleep reset
Enabling EXT1 wakeup on pins GPIO2, GPIO4
Entering deep sleep
ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x1 (POWERON),boot:0xb (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fcd0108,len:0x1714
load:0x403b6000,len:0xb7c
load:0x403ba000,len:0x3094
entry 0x403b6248
I (24) boot: ESP-IDF v4.4.1-dirty 2nd stage bootloader
I (25) boot: compile time 10:52:31
I (25) boot: chip revision: 0
I (27) boot.esp32s3: Boot SPI Speed : 80MHz
I (32) boot.esp32s3: SPI Mode : DIO
I (36) boot.esp32s3: SPI Flash Size : 2MB
I (41) boot: Enabling RNG early entropy source...
I (47) boot: Partition Table:
I (50) boot: ## Label Usage Type ST Offset Length
I (57) boot: 0 nvs WiFi data 01 02 00009000 00006000I (65) boot: 1 phy_init RF data 01 01 0000f000 00001000I (72) boot: 2 factory factory app 00 00 00010000 00100000I (80) boot: End of partition table
I (84) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=07f50h (
32592) map
I (98) esp_image: segment 1: paddr=00017f78 vaddr=3fc91e60 size=02774h (
10100) load
I (103) esp_image: segment 2: paddr=0001a6f4 vaddr=40374000 size=05924h ( 22820) load
I (114) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=1778ch ( 96140) map
I (135) esp_image: segment 4: paddr=000377b4 vaddr=40379924 size=08530h ( 34096) load
I (143) esp_image: segment 5: paddr=0003fcec vaddr=50000000 size=00010h ( 16) load
I (143) esp_image: segment 6: paddr=0003fd04 vaddr=600fe000 size=00028h ( 40) load
I (155) boot: Loaded app from partition at offset 0x10000
I (155) boot: Disabling RNG early entropy source...
I (172) cpu_start: Pro cpu up.
I (172) cpu_start: Starting app cpu, entry point is 0x403751e8
0x403751e8: call_start_cpu1 at H:/ESP32/Espressif/frameworks/esp-idf-v4.4.1/esp-idf-v4.4.1/components/esp_system/port/cpu_start.c:160

I (0) cpu_start: App cpu up.
I (186) cpu_start: Pro cpu start user code
I (186) cpu_start: cpu freq: 160000000
I (186) cpu_start: Application information:
I (189) cpu_start: Project name: deep_sleep
I (194) cpu_start: App version: 1
I (199) cpu_start: Compile time: Oct 19 2022 10:51:47
I (205) cpu_start: ELF file SHA256: d221e5cbd6a9a6da...
I (211) cpu_start: ESP-IDF: v4.4.1-dirty
I (216) heap_init: Initializing. RAM available for dynamic allocation:
I (223) heap_init: At 3FC94FD8 len 0004B028 (300 KiB): D/IRAM
I (230) heap_init: At 3FCE0000 len 0000EE34 (59 KiB): STACK/DRAM
I (236) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
I (243) heap_init: At 600FE028 len 00001FC8 (7 KiB): RTCRAM
I (249) spi_flash: detected chip: generic
I (254) spi_flash: flash io: dio
W (257) spi_flash: Detected size(8192k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
I (271) sleep: Configure to isolate all GPIO pins in sleep state
I (278) sleep: Enable automatic switching of GPIO sleep configuration
I (285) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
core 0: 01 core 1: 01
Not a deep sleep reset
Enabling EXT1 wakeup on pins GPIO2, GPIO4
Entering deep sleep



It seems that triggering ext1 wakeup will cause this problem, but I'm not sure.
The code is as follows：
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_sleep.h"
#include "esp_log.h"
#include "driver/rtc_io.h"
#include "rom/rtc.h"


void app_main(void)
{
printf("core 0: %02x\tcore 1: %02x\r\n", rtc_get_reset_reason(0), rtc_get_reset_reason(1));
switch (esp_sleep_get_wakeup_cause()) {
#ifdef CONFIG_EXAMPLE_EXT1_WAKEUP
case ESP_SLEEP_WAKEUP_EXT1: {
uint64_t wakeup_pin_mask = esp_sleep_get_ext1_wakeup_status();
if (wakeup_pin_mask != 0) {
int pin = __builtin_ffsll(wakeup_pin_mask) - 1;
printf("Wake up from GPIO %d\n", pin);
} else {
printf("Wake up from GPIO\n");
}
break;
}
#endif // CONFIG_EXAMPLE_EXT1_WAKEUP
case ESP_SLEEP_WAKEUP_UNDEFINED:
default:
printf("Not a deep sleep reset\n");
}

vTaskDelay(1000 / portTICK_PERIOD_MS);
#ifdef CONFIG_EXAMPLE_EXT1_WAKEUP
const int ext_wakeup_pin_1 = 2;
const uint64_t ext_wakeup_pin_1_mask = 1ULL << ext_wakeup_pin_1;
const int ext_wakeup_pin_2 = 4;
const uint64_t ext_wakeup_pin_2_mask = 1ULL << ext_wakeup_pin_2;
printf("Enabling EXT1 wakeup on pins GPIO%d, GPIO%d\n", ext_wakeup_pin_1, ext_wakeup_pin_2);
esp_sleep_enable_ext1_wakeup(ext_wakeup_pin_1_mask | ext_wakeup_pin_2_mask, ESP_EXT1_WAKEUP_ANY_HIGH);
#endif // CONFIG_EXAMPLE_EXT1_WAKEUP
printf("Entering deep sleep\n");
esp_deep_sleep_start();
}


I don't see any record of this in the 4.4.2 update in github, so if any of you know why, please let me know.