Questions about SPI timing etc.

[permal]

Hi,

Attempting my first ever implementation of SPI to communication with a TFT display driven by a ST7735 using 4-wire SPI.

A few questions regarding spi_device_interface_config_t:

The following three values, they actually specify a delay, right? For example, with clock_speed_hz = 2000000 (2MHz), a value of 16 would give a delay of 16 * 1/2000000 = 8ns. I assume these are used to fulfill the timing requirements for the device in question?
- dummy_bits
- cs_ena_pretrans
- cs_ena_posttrans

For example, on page 25; section 8.3 Tacc (read) is specified at 10-50ns, meaning I need to set dummy_bits to 20 to guarantee 10nS (with a clock_speed_hz @2Mhz)? Or am I overdoing it and I can just assume that if the device follows the SPI spec, things will work as expected?

According to the documentation command_bits & address_bits specifies whether or not the "command phase" or "address phase" should be performed. This confuses me a little when looking at the SPI master example, line 259 since it doesn't set these values, but still sends commands to the device.

Is it that some SPI devices require every transaction to be prefixed with a command and/or address and the IDF-driver provides this capability through these settings?

When specifying SPI_DEVICE_3WIRE for the flags value, shouldn't SPI_DEVICE_HALFDUPLEX be implicitly activated or are there devices which have one-way communication?