QuadSPI - cannot change ADDR & DUMMY lengths in slave mode
Posted: Thu Mar 24, 2022 6:49 pm
I'm using the SPI peripheral as a slave in QPI mode. By default, the ADDR phase is 1-byte and DUMMY is 2 bytes, both in 4-bit mode, for a total of 6 SPI Clock periods. This is as per the datasheet (Table 138, Section 24.5.3 GP-SPI2 Slave Mode Single Transfer) and also matches my observations (e.g. it's working).
I would really like to extend the DUMMY period to 6 bytes (adding 8 more clock cycles) but am unable to do so. Modifying 'usr_dummy_cyclelen' in the USER1 register has no effect. I also tried extending the ADDR phase through changing 'usr_addr_bitlen' in the USER1 register as well - zero impact. Is there a different way to do this?
I would really like to extend the DUMMY period to 6 bytes (adding 8 more clock cycles) but am unable to do so. Modifying 'usr_dummy_cyclelen' in the USER1 register has no effect. I also tried extending the ADDR phase through changing 'usr_addr_bitlen' in the USER1 register as well - zero impact. Is there a different way to do this?