tobewinner wrote:
1, what is the differences between esp_intr_disable/esp_intr_enable and xt_ints_off/xt_ints_on?
esp_intr_disable/enable functions' argument is an opaque handle returned by esp_intr_alloc. For xt_ints_off/on, the argument is a 32-bit interrupt mask. You should not use xt_ints_off/on for interrupts allocated using esp_intr_alloc.
Another difference is that xt_ints_off always masks interrupts via CPU's INTENABLE register. As such, xt_ints_off can disable interrupts on the current CPU only. esp_intr_disable masks CPU internal interrupts (such as timer compare and profiling interrupts) using INTENABLE, while external interrupts (coming from peripherals) are masked using interrupt matrix. This allows disabling external interrupts routed to a CPU even if esp_intr_disable is called from the other CPU.
tobewinner wrote:
2, As we know, ESP32 is a cpu with 2 cores, if the interrupt callback in running an a core, and the other core calls esp_intr_disable or xt_ints_off, will the func(esp_intr_disable or xt_ints_off) not return untill the running callback returns?
You can not call xt_ints_off to disable interrupts of the other CPU. xt_ints_off/on only affect INTENABLE register of the CPU where they are called.
esp_intr_disable returns immediately, it does not wait for other CPU to do interrupt handling.
tobewinner wrote:
3, If the interrupt event occurs during the period that the orresponding interrupt is masked by esp_intr_disable(or xt_ints_off), will the callback be called after esp_intr_enalbe(or xt_ints_on)?
This depends on the specific interrupt type. Edge triggered interrupts will not be dispatched if they happen when interrupt is disabled. Level triggered interrupts are normally latched on the peripheral side, and need to be cleared explicitly by writing to interrupt clear register of the peripheral; therefore they will be dispatched as soon as you re-enable the interrupt.