ESP32 Forum

Have a DevkitM esp32-s2-mini-1U with a ENC28J60 module connected using the GPIO pin configuration with short ~5cm jumper wires:
CS0 15
SCLK 14
MISO 12
MOSI 13
Interrupt 4
3.3V from devkitM to the ethernet module

idf.py menuconfig uses the above configuration, with SPICLK speed set to 5 MHZ.

I get the following error when teh devkitM boots up:
(442) cpu_start: Starting scheduler on PRO CPU.
I (444) gpio: GPIO[4]| InputEn: 0| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
I (454) enc28j60: revision: 0
E (454) enc28j60: enc28j60_verify_id(480): wrong chip ID
E (454) enc28j60: emac_enc28j60_init(854): vefiry chip ID failed
I (464) gpio: GPIO[4]| InputEn: 0| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
E (474) esp_eth: esp_eth_driver_install(203): init mac failed
ESP_ERROR_CHECK failed: esp_err_t 0xffffffff (ESP_FAIL) at 0x40025e58
0x40025e58: _esp_error_check_failed at /home/achu/esp/esp-idf/components/esp_common/src/esp_err.c:41

file: "../main/enc28j60_example_main.c" line 117
func: app_main


Has anybody verified devkitM + ENC28j60. Has this example run in other modules and if so can somebody help verify whether the above is expected to work.


Complete output:
[Codebox] P-ROM:esp32s2-rc4-20191025
Build:Oct 25 2019
rst:0x1 (POWERON),boot:0x9 (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:DIO, clock div:4
load:0x3ffe6100,len:0x8
load:0x3ffe6108,len:0x180c
load:0x4004c000,len:0x9d0
load:0x40050000,len:0x2e30
entry 0x4004c1ec
I (60) boot: ESP-IDF v4.3-dev-1720-g494a124d9 2nd stage bootloader
I (60) boot: compile time 15:42:04
I (60) boot: chip revision: 0
I (64) boot.esp32s2: SPI Speed : 20MHz
I (68) boot.esp32s2: SPI Mode : DIO
I (73) boot.esp32s2: SPI Flash Size : 2MB
I (78) boot: Enabling RNG early entropy source...
I (83) boot: Partition Table:
I (87) boot: ## Label Usage Type ST Offset Length
I (94) boot: 0 nvs WiFi data 01 02 00009000 00006000
I (101) boot: 1 phy_init RF data 01 01 0000f000 00001000
I (109) boot: 2 factory factory app 00 00 00010000 00100000
I (117) boot: End of partition table
I (121) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f000020 size=0x0fb90 ( 64400) map
I (157) esp_image: segment 1: paddr=0x0001fbb8 vaddr=0x3ffbe3c0 size=0x00460 ( 1120) load
I (158) esp_image: segment 2: paddr=0x00020020 vaddr=0x40080020 size=0x301dc (197084) map
0x40080020: _stext at ??:?

I (246) esp_image: segment 3: paddr=0x00050204 vaddr=0x3ffbe820 size=0x022b8 ( 8888) load
I (250) esp_image: segment 4: paddr=0x000524c4 vaddr=0x40022000 size=0x00404 ( 1028) load
0x40022000: _WindowOverflow4 at /home/achu/esp/esp-idf/components/freertos/xtensa/xtensa_vectors.S:1730

I (253) esp_image: segment 5: paddr=0x000528d0 vaddr=0x40022404 size=0x0bfb4 ( 49076) load
0x40022404: _coredump_iram_start at ??:?

I (291) boot: Loaded app from partition at offset 0x10000
I (291) boot: Disabling RNG early entropy source...
I (303) cache: Instruction cache : size 8KB, 4Ways, cache line size 32Byte
I (303) cpu_start: Pro cpu up.
I (358) cpu_start: Pro cpu start user code
I (358) cpu_start: cpu freq: 160000000
I (358) cpu_start: Application information:
I (361) cpu_start: Project name: enc28j60
I (366) cpu_start: App version: 1
I (371) cpu_start: Compile time: Nov 15 2020 15:42:02
I (377) cpu_start: ELF file SHA256: 843475f919653822...
[/Codebox]

ENC29J60 revision reads out "0", one possibility could be the SPI communication is wrong (wrong wiring? SPI timing setting?)

Verified the wirings and the build config, no luck.
If you or members of this forum can recommend the module or breakout board that is commonly used to add ethernet support that would suffice too. Any purchase links to actual ethernet PHY boards is very much appreciated.
Thanks all.