ESP32 Forum

rtc_clk_apll_enable函数调用
总是处于循环中无法结束
/* wait for calibration end */
while (!(I2C_READREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_CAL_END))) {
/* use ets_delay_us so the RTC bus doesn't get flooded */
ets_delay_us(1);
}
请问如何解决

Thanks for the report. What argument values are you passing to rtc_clk_apll_enable?

ESP_igrr wrote:Thanks for the report. What argument values are you passing to rtc_clk_apll_enable?

rtc_clk_apll_enable(true, 0, 0, 1, 0);

REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1);
...

类似这个寄存器操作不正确，但是又没有寄存器说明

It should probably be instead.

ESP_igrr wrote:It should probably be

Code: Select all

    SET_PERI_REG_BITS(RTC_CNTL_ANA_CONF_REG, 1, enable ? 0 : 1, RTC_CNTL_PLLA_FORCE_PD_S);
    SET_PERI_REG_BITS(RTC_CNTL_ANA_CONF_REG, 1, enable ? 1 : 0, RTC_CNTL_PLLA_FORCE_PU_S);
    SET_PERI_REG_BITS(RTC_CNTL_OPTIONS0_REG, 1, enable ? 0 : 1, RTC_CNTL_BIAS_I2C_FORCE_PD_S);

instead.

不单单是这几个寄存器，这三个寄存器的值我修改过，但是仍然无法跳出循环，可能还有其他地方类似需要使能的时候，用错函数，导致寄存器操作失败

With the above change rtc_clk_apll_enable works well both on rev0 and rev1 chips.

The reason why rtc_clk_apll_enable(true, 0, 0, 1, 0) doesn't work is that the arguments don't meet the range given in the function documentation:

apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2)

The dividend in this expression should be in the range of 240 - 600 MHz.

With sdm2 = 1, the dividend is 200 MHz.

So for 50mhz we want rtc_clk_apll_enable(true, 0, 0, 6, 2)?

That's correct, rtc_clk_apll_enable(true, 0, 0, 6, 2) gives 50 MHz output.

ESP_igrr wrote:That's correct, rtc_clk_apll_enable(true, 0, 0, 6, 2) gives 50 MHz output.

已经搞定万分感谢

@ESP_igrr: I saw the new sources for clock management (https://github.com/espressif/esp-idf/bl ... clk.c#L120), its for I2C and not for I2S, right?