SPI transmission repetition rate
Posted: Tue Mar 07, 2017 2:17 pm
In my application I need to send a series of 16-bit wide SPI commands to some slave devices (A/D converters). Since the chip-select line is used to initiate ADC sampling I need to send command at a given repetition rate (i.e. every 1.5us) with a serial clock speed of 20MHz like in the diagram below.
The only way to send commands with standard SPI pattern (chip select assertion, shift-out word bits and chip-select de-assertion) seems to load the command word in the SPI transaction structure each time. The SPI diver offers two transmission variants: synchronous and queued.
Using the synchronous transmit (i.e. a single queue/get) the command repetition rate is more than 40us (but constant) between two consecutive transmit.
(yellow: sync signal, green: chip-select, violet: serial clock, red: MOSI)
Using the queue/get transmit (i.e. queue all transmit then get queue results) the command repetition rate varies between 10us and 19us (and so not constant) between two consecutive transmit.
(yellow: sync signal, green: chip-select, violet: serial clock, red: MOSI)
It looks like a pity having the SPI clock reach high speed (i.e. up to 80MHz) but having the driver to send commands only at 100kHz (best case).
My question: Is it possible to implement a sort of burst transfer (i.e. from a buffer) to transmit command words (with chip-select assertion/de-assertion) at a higher repetition rate? (i.e. sending 140 command words at 4kHz)
Note: SPI clock speed is currently set to 10MHz.
Hint: Sending 16-bit word using the internal buffer of the SPI transaction structure it is required to load the low byte in tx_data[1] and the high byte in tx_data[0] to respect the correct bit order (e.g. MSB first).
The only way to send commands with standard SPI pattern (chip select assertion, shift-out word bits and chip-select de-assertion) seems to load the command word in the SPI transaction structure each time. The SPI diver offers two transmission variants: synchronous and queued.
Using the synchronous transmit (i.e. a single queue/get) the command repetition rate is more than 40us (but constant) between two consecutive transmit.
(yellow: sync signal, green: chip-select, violet: serial clock, red: MOSI)
Using the queue/get transmit (i.e. queue all transmit then get queue results) the command repetition rate varies between 10us and 19us (and so not constant) between two consecutive transmit.
(yellow: sync signal, green: chip-select, violet: serial clock, red: MOSI)
It looks like a pity having the SPI clock reach high speed (i.e. up to 80MHz) but having the driver to send commands only at 100kHz (best case).
My question: Is it possible to implement a sort of burst transfer (i.e. from a buffer) to transmit command words (with chip-select assertion/de-assertion) at a higher repetition rate? (i.e. sending 140 command words at 4kHz)
Note: SPI clock speed is currently set to 10MHz.
Hint: Sending 16-bit word using the internal buffer of the SPI transaction structure it is required to load the low byte in tx_data[1] and the high byte in tx_data[0] to respect the correct bit order (e.g. MSB first).