UART driver low level detals and false break detect
Posted: Sat Dec 21, 2019 2:50 pm
Is there anyone here who has detailed knowledge of the inner workings of the uart driver?
Any guru's about?
I am having problems receiving a 512 byte broadcast.
It returns a break detect status after 480 bytes (it is receiving them 120 at a time). It does receive the first 360 bytes, but at that point the break detect is received and there are and additional 120 bytes in the receive buffer and another 32 bytes should arrive before the next break. (This is confirmed by watching the serial stream on a logic analyzer.)
There is a define in the uart.c:
I'm guessing this is why the driver is returning 120 at a time. But, I can't see anything that would indicate why there would be a false break detect.
Any guru's about?
I am having problems receiving a 512 byte broadcast.
It returns a break detect status after 480 bytes (it is receiving them 120 at a time). It does receive the first 360 bytes, but at that point the break detect is received and there are and additional 120 bytes in the receive buffer and another 32 bytes should arrive before the next break. (This is confirmed by watching the serial stream on a logic analyzer.)
There is a define in the uart.c:
Code: Select all
#define UART_FULL_THRESH_DEFAULT (120)