Flashing plain text firmware after encryption while development
Posted: Sun Nov 03, 2019 9:45 am
Hi,
I am trying the flash encryption now. I am not using secure boot for now.
I am using esp-idf 3.3 (latest stable) in linux.
In menuconfig -> Security features I enabled Enable flash encryption on boot (READ DOCS FIRST)
Since I am developing I entered into Potentially insecure options ---> and enabled
[*] Allow JTAG Debugging
[*] Leave UART bootloader encryption enabled
[*] Leave UART bootloader decryption enabled
[*] Leave UART bootloader flash cache enabled
Now I did make flash and the firmware is downloaded and encrypted by the chip on first boot.
a
Now I am unable to load plain text firmware for development purpose, because I thought if I check [*] Leave UART bootloader encryption enabled , [*] Leave UART bootloader decryption enabled and [*] Leave UART bootloader flash cache enabled then I can force the esp32 to encrypt and save the bootloader firmware loaded via serial bootloader. But this is not the case. Chip is on bootloop reset after doing subsequent "make flash".
For development, I can insert pre-defined 32bit encryption key, but in this case I haven't done that by assuming that if I prevent DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE to be burned '1'.
So what exactly is the function of these bits ?
My espefuse.py summary is as below.
I am trying the flash encryption now. I am not using secure boot for now.
I am using esp-idf 3.3 (latest stable) in linux.
In menuconfig -> Security features I enabled Enable flash encryption on boot (READ DOCS FIRST)
Since I am developing I entered into Potentially insecure options ---> and enabled
[*] Allow JTAG Debugging
[*] Leave UART bootloader encryption enabled
[*] Leave UART bootloader decryption enabled
[*] Leave UART bootloader flash cache enabled
Now I did make flash and the firmware is downloaded and encrypted by the chip on first boot.
a
Now I am unable to load plain text firmware for development purpose, because I thought if I check [*] Leave UART bootloader encryption enabled , [*] Leave UART bootloader decryption enabled and [*] Leave UART bootloader flash cache enabled then I can force the esp32 to encrypt and save the bootloader firmware loaded via serial bootloader. But this is not the case. Chip is on bootloop reset after doing subsequent "make flash".
Code: Select all
[15:21:05:366] rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)␍␊
[15:21:05:366] flash read err, 1000␍␊
[15:21:05:366] ets_main.c 371 ␍␊
[15:21:05:762] ets Jun 8 2016 00:22:57␍␊
So what exactly is the function of these bits ?
My espefuse.py summary is as below.
Code: Select all
espefuse.py v2.7-dev
Connecting........_
EFUSE_NAME Description = [Meaningful Value] [Readable/Writeable] (Hex Value)
----------------------------------------------------------------------------------------
Security fuses:
FLASH_CRYPT_CNT Flash encryption mode counter = 7 R/W (0x7)
FLASH_CRYPT_CONFIG Flash encryption config (key tweak bits) = 15 R/W (0xf)
CONSOLE_DEBUG_DISABLE Disable ROM BASIC interpreter fallback = 1 R/W (0x1)
ABS_DONE_0 secure boot enabled for bootloader = 0 R/W (0x0)
ABS_DONE_1 secure boot abstract 1 locked = 0 R/W (0x0)
JTAG_DISABLE Disable JTAG = 0 R/W (0x0)
DISABLE_DL_ENCRYPT Disable flash encryption in UART bootloader = 0 R/W (0x0)
DISABLE_DL_DECRYPT Disable flash decryption in UART bootloader = 0 R/W (0x0)
DISABLE_DL_CACHE Disable flash cache in UART bootloader = 0 R/W (0x0)
BLK1 Flash encryption key
= ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? -/-
BLK2 Secure boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLK3 Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
Efuse fuses:
WR_DIS Efuse write disable mask = 128 R/W (0x80)
RD_DIS Efuse read disablemask = 1 R/W (0x1)
CODING_SCHEME Efuse variable block length scheme = 0 R/W (0x0)
KEY_STATUS Usage of efuse block 3 (reserved) = 0 R/W (0x0)
Config fuses:
XPD_SDIO_FORCE Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = 0 R/W (0x0)
XPD_SDIO_REG If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = 0 R/W (0x0)
XPD_SDIO_TIEH If XPD_SDIO_FORCE & XPD_SDIO_REG, 1=3.3V 0=1.8V = 0 R/W (0x0)
CLK8M_FREQ 8MHz clock freq override = 54 R/W (0x36)
SPI_PAD_CONFIG_CLK Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0x0)
SPI_PAD_CONFIG_Q Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0x0)
SPI_PAD_CONFIG_D Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0x0)
SPI_PAD_CONFIG_HD Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0x0)
SPI_PAD_CONFIG_CS0 Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0x0)
DISABLE_SDIO_HOST Disable SDIO host = 0 R/W (0x0)
Identity fuses:
MAC Factory MAC Address
= 39:54:a4:c3:65:1c (CRC e8 OK) R/W
CHIP_VER_REV1 Silicon Revision 1 = 0 R/W (0x0)
CHIP_VERSION Reserved for future chip versions = 0 R/W (0x0)
CHIP_PACKAGE Chip package identifier = 0 R/W (0x0)
Calibration fuses:
BLK3_PART_RESERVE [Codebox=bash file=Untitled.bsh][/Codebox] BLOCK3 partially served for ADC calibration data = 0 R/W (0x0)
ADC_VREF Voltage reference calibration = 1100 R/W (0x0)
Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).