SPI timing violation using hardware chip-select

[luca.gamma]

Configuring the SPI master peripheral (HSPI) I require at least half bit-cycle after transmission before the chip-select becomes inactive. The SPI device interface configuration structure has a member called 'cs_ena_posttrans' which should be set to the number of bit-cycle to wait. Actually setting this member to 0 the CS rise just after the last transmission clock but setting to 1 the timing doesn't change. To add 1 bit-cycle I had to set the value to 2 or 3 to wait for 2 bit-cycles and so on. Is this a bug or is it in some way the desired behaviour?

[WiFive]

Seems like bug as TRM doesn't say number of cycles minus one but that is what driver uses

[ESP_Sprite]

Huh, may be my bad. I'll look into it.