Allocate 2 buffers in specific address at different memory banks

[ESP_houwenxiang]

Hi, Baldhead

Thank you for your suggestion. Due to hardware limitations, the DMA transfer data size is at least one word long. Can you provide an LCD data sheet, maybe we can use 16-bit mode to drive it.

thanks !!

[Baldhead]

Hi,

With 16 bits many pins of esp32 chip are used.

With 16 bits is possible to transfer a uint16_t buffer directly to i2s module with dma ?
Without to copy the uint16_t buffer to another uint32_t buffer ?

Even so would be a 50% memory waste and the time taken to copy the buffer.

Thank's.

[Baldhead]

Hi,

"Thank you for your suggestion. Due to hardware limitations, the DMA transfer data size is at least one word long. Can you provide an LCD data sheet, maybe we can use 16-bit mode to drive it."

The fifo receive one word wide(32bits) by dma but the fifo pointer could be byte wide.

Thank's.

[Baldhead]

Hi,

I am not a expert, but i will suggest the following, i dont know if it is possible.

Fifo input:
DMA tranfer size 32 bits.

Word size in bits: 8, 16, 24, 32, 64.
Least common multiple( 8, 16, 24, 32, 64 ) = 192.
Fifo size in bytes unity = 192, 384, 576, 768, ... , 192 * N. N integer diferent from zero.

Fifo output:
Dependent on io config maybe or another parameter ???
Need one more information: transfer size(already exist in dma descriptor with the name lenght).
example:
If ( 8bits ), dma transfer 4 bytes per "bus transaction", transfer lenght = 1, so, fifo will transfer one single byte and so on.


If ( 8 bits ) Fifo address pointer increment or decrement = 1 position per transfer lenght.

If ( 16 bits ) Fifo address pointer increment or decrement = 2 position per transfer lenght.

If ( 24 bits ) Fifo address pointer increment or decrement = 3 position per transfer lenght.

If ( 32 bits ) Fifo address pointer increment or decrement = 4 position per transfer lenght.

If ( 64 bits ) Fifo address pointer increment or decrement = 8 position per transfer lenght.


Thank's.

[ESP_houwenxiang]

Hi, Baldhead

The I2S DMA of ESP32 only have 16 bit or 32 bit mode, and the DMA length should be at least 4 byte length. .e.g:

If the DMA buffer is 4 byte length and is filled with 0x12345678, when the `bit_mode = 8`, you will see 0x34, 0x78 appear on the bus.

which means data on the line is always 2*N bytes. But some LCD only need one byte command or one byte data. I know an NT35510 LCD driver chip. Its data and commands are always 2 bytes(.e.g. Display On command (0x2900h)). We can use I2S 8-bit mode to drive it, but I don't know which driver chip your LCD uses. So I ask you the manual of your LCD.

thanks !!

[Baldhead]

Hi,

I want to use a display with R61529 controller in 8 bits parallel mode.

In annex follow the datasheet of R61529.

I opened a technical inquire a few days ago, and i attached some files ( my i2s driver that is not working and other files ).

I fixed some bugs of my i2s driver after sending the files in technical inquire, but not working yet.
link: "viewtopic.php?f=12&t=13274"

I would like to use my driver.

If you want i can send the corrected files again in some private way if possible.

You are part of the espressif team ( work on espressif ) ?


Thank's.

[ESP_houwenxiang]

Hi, Baldhead

Sorry that the ESP32 I2S DMA cannot meet your needs. To drive this LCD, you can only use 32-bit mode, and you need to convert bytes to words. But our upcoming ESP32-S2 can drive your LCD well.

[Baldhead]

Hi ESP_houwenxiang,

Actually i would be pretty happy to make my i2s driver work with dma.

"viewtopic.php?f=12&t=13274".


Thank's.

[Baldhead]

Hi ESP_houwenxiang,


I forgot to say that this was a suggestion for possible new hardware ( new chip or new chip module(independent generic dma, i2s, ...) ).




"Hi,

I am not a expert, but i will suggest the following, i dont know if it is possible.

Fifo input:
DMA tranfer size 32 bits.

Word size in bits: 8, 16, 24, 32, 64.
Least common multiple( 8, 16, 24, 32, 64 ) = 192.
Fifo size in bytes unity = 192, 384, 576, 768, ... , 192 * N. N integer diferent from zero.

Fifo output:
Dependent on io config maybe or another parameter ???
Need one more information: transfer size(already exist in dma descriptor with the name lenght).
example:
If ( 8bits ), dma transfer 4 bytes per "bus transaction", transfer lenght = 1, so, fifo will transfer one single byte and so on.


If ( 8 bits ) Fifo address pointer increment or decrement = 1 position per transfer lenght.

If ( 16 bits ) Fifo address pointer increment or decrement = 2 position per transfer lenght.

If ( 24 bits ) Fifo address pointer increment or decrement = 3 position per transfer lenght.

If ( 32 bits ) Fifo address pointer increment or decrement = 4 position per transfer lenght.

If ( 64 bits ) Fifo address pointer increment or decrement = 8 position per transfer lenght.


Thank's."