Latest MCPWM working different compared to ESP-IDF revision 4.2

[Vaskov]

Hi,

I had previously configured and successfully used MCPWM module. However, now when I updated to the master, I am having problem that I am getting pwm outputted from both outputs for motor 1 instead of only one (I am setting in code to have 30% duty cycle in mcpwm0a and 0% for mcpwm0b if my understanding is correct - at least it worked before for rev4.2) . Configuration code:

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#define GPIO_NA1 	GPIO_NUM_25    //Set GPIO 25 as NA1 output
#define GPIO_NA2 	GPIO_NUM_26    //Set GPIO 26 as NA2 output

#define GPIO_NB1 	GPIO_NUM_18    //Set GPIO 25 as NB1 output
#define GPIO_NB2 	GPIO_NUM_5     //Set GPIO 26 as NB2 output

    // Init GPIO
    mcpwm_pin_config_t pin_config = {
        GPIO_NA1,           // mcpwm0a_out_num         /*!<MCPWM0A out pin*/
        GPIO_NA2,           // mcpwm0b_out_num         /*!<MCPWM0B out pin*/
        GPIO_NB1,           // mcpwm1a_out_num         /*!<MCPWM1A out pin*/
        GPIO_NB2,           // mcpwm1b_out_num         /*!<MCPWM1B out pin*/
        GPIO_NC1,           // mcpwm2a_out_num         /*!<MCPWM2A out pin*/
        GPIO_NC2,           // mcpwm2b_out_num         /*!<MCPWM2B out pin*/
        -1,                 // mcpwm_sync0_in_num      /*!<SYNC0  in pin*/
        -1,                 // mcpwm_sync1_in_num      /*!<SYNC1  in pin*/
        -1,                 // mcpwm_sync2_in_num      /*!<SYNC2  in pin*/
        -1,                 // mcpwm_fault0_in_num     /*!<FAULT0 in pin*/
        -1,                 // mcpwm_fault1_in_num     /*!<FAULT1 in pin*/
        -1,                 // mcpwm_fault2_in_num     /*!<FAULT2 in pin*/
        -1,                 // mcpwm_cap0_in_num       /*!<CAP0   in pin*/
        -1,                 // mcpwm_cap1_in_num       /*!<CAP1   in pin*/
        -1                  // mcpwm_cap2_in_num       /*!<CAP2   in pin*/
    };

    mcpwm_set_pin(MCPWM_UNIT_0, &pin_config);

    mcpwm_config_t pwm_config = {
        50000,              // frequency    /*!<Set frequency of MCPWM in Hz*/
        0.0,                // cmpr_a       /*!<Set % duty cycle for operator a(MCPWMXA), i.e for 62.3% duty cycle, duty_a = 62.3*/
        0.0,                // cmpr_b       /*!<Set % duty cycle for operator b(MCPWMXB), i.e for 48% duty cycle, duty_b = 48.0*/
        MCPWM_DUTY_MODE_0,  // duty_mode    /*!<Set type of duty cycle*/
        MCPWM_UP_COUNTER    // counter_mode /*!<Set  type of MCPWM counter*/
    };

    mcpwm_init(MCPWM_UNIT_0, MCPWM_TIMER_0, &pwm_config); //Configure PWM0A & PWM0B with above settings
    mcpwm_start(MCPWM_UNIT_0, MCPWM_TIMER_0);

    mcpwm_init(MCPWM_UNIT_0, MCPWM_TIMER_1, &pwm_config); //Configure PWM1A & PWM1B with above settings
    mcpwm_start(MCPWM_UNIT_0, MCPWM_TIMER_1);

    mcpwm_set_duty(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_GEN_B, 0);
    mcpwm_set_duty(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_GEN_A, 30);

    mcpwm_set_duty(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_GEN_A, 0);
    mcpwm_set_duty(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_GEN_B, 0);

    // Enable deadtime
    mcpwm_deadtime_enable(MCPWM_UNIT_0, MCPWM_TIMER_0, MCPWM_ACTIVE_HIGH_MODE, 10, 10);
    mcpwm_deadtime_enable(MCPWM_UNIT_0, MCPWM_TIMER_1, MCPWM_ACTIVE_HIGH_MODE, 10, 10);

When checking pins GPIO_NA1 and GPIO_NA2 on Logic analyser this is what I get:

[ESP_morris]

I think this is a bug in the previous driver, so we have corrected it. The definition of "Active High" is

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MCPWM_ACTIVE_HIGH_MODE,             /*!<MCPWMXA Out = MCPWMXA In with rising edge delay,  MCPWMXB Out = MCPWMXA In with falling edge delay*/

This means, you only need to configure MCPWMA, and MCPWMB will derive from MCPWMA plus a deadtime.

This diagram should explain it:

explain dead time of MCPWM

2021-10-28_17-29.png (42.68 KiB) Viewed 1952 times