I'm using the ESP32-WROVER-B board, which itself uses the Xtensa LX6 microprocessor. From their Overview Handbook, I learned that the Xtensa LX processor family supports some specialized extensions to their instruction set. They include "zero-overhead" loops and min/max hardware-level implementations (compare section 2.12.1 http://loboris.eu/ESP32/Xtensa_lx%20Ove ... G8.1098890). Unfortunately, I couldn't directly find out whether the ESP32 boards include these features. Neither from the comparison table in the documentation (https://docs.espressif.com/projects/esp ... rison.html) nor from the data sheet (https://www.espressif.com/sites/default ... eet_en.pdf).
However what I found were the configurations for the binutils overlays, where the loop and minmax features are enabled (compare https://github.com/espressif/xtensa-ove ... nfig.h#L71). This is true for the ESP-IDF toolchain I downloaded, as well (check
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$IDF_TOOLS_PATH/tools/xtensa-esp32-elf/esp-2021r1-8.4.0/xtensa-esp32-elf/sys-include/xtensa/config/core-isa.h
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xtensa_lx106
In theory these features should be available, but when I check the code generated from gcc, I don't see any of those op codes in the assembly listing. Even when I use the
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-O2
I get the following assembly for a
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int x = (a < b) ? a : b;
- # a and b are set before
- # ...
- blt a11, a2, .L49
- bne a2, a11, .L48
- bgeu a10, a3, .L48
- # ...
- # ...
- j .L4
- .L5:
- # loop body
- # ...
- .L4:
- blt a7, a4, .L5
- # ...