New ESP32 Board Bootloader

[chegewara]

On this schematic you can see that flash and psram share SCK/CLK pin, but signal is split with additional R 0ohm resistors, so it could be possible to use separate clock signals if needed.

[lannocm]

So, should I be using the same clock or the separate clock for the flash? Does it matter?

And does anyone know what /CS and /HOLD etc is?

[WiFive]

It should work as long as esp-idf supports shared clock. Slash in front of signal name just means active low.

[lannocm]

Hi,

You may remember I was having issues with the designer. I finally got my money back but I want to use the design as the basis of version 2, if possible. The first design didn't have flash, so, I guess I have a couple of options.

a) add external flash
b) use an ESP chip that includes flash.

Option a means more space, so I'm inclined to go with option b, which means D2WD or U4WDH, according to the table below, which also has a smaller footprint than the D0WD.

So, should I be going for cores over memory or vice versa?

Thanks

Identifier cores flash(MB) size
ESP31B 2 0 6 mm×6 mm Pre-release SoC used for beta testing; no longer available.
ESP32-D0WDQ6 2 0 6 mmx6mm Initial production release chip of the ESP32 series.
ESP32-D0WD 2 0 5 mm×5 mm Smaller physical package variation similar to ESP32-D0WDQ6.
ESP32‑D2WD 2 2 5 mm×5 mm 2 MiB (16 Mibit) embedded flash memory variation.
ESP32-U4WDH 1 4 5 mm×5 mm Single-core processor and 4 MiB (32 Mibit) embedded flash memory variation.
ESP32‑S0WD 1 0 5 mm×5 mm Single-core processor variation.

[WiFive]

If you really want to save space ESP32-PICO-V3-02 assuming you don't need more than 2mb psram