Before waking up the ESP32 ULP from deep sleep, the documentation explains how and why to check the RTC_CNTL_RDY_FOR_WAKEUP bit before executing the wake instruction. None of the documentation explains what causes that bit to be set or cleared.
I am using the ULP in a battery powered system to do periodic monitoring of several sensors. Before the main processor is woken to process this data, several high energy drain subsystems have to be powered up for FreeRTOS to see while it boots. I don't want to energise the subsystems until I know the processor can be woken because of the cumulative effect on battery life. Therefore, there is a window measured in ms between the time the bit is sampled high, and the wake instruction is executed.
If I know the possible reasons for RTC_CNTL_RDY_FOR_WAKEUP to be set/cleared, I can decide whether it makes sense to spin waiting for the bit to flip (as the demo code does) or to halt and check again on the next sensor sweep.
I have three questions about RTC_CNTL_RDY_FOR_WAKEUP that I can't find the answer to:
- what causes the RTC_CNTL_RDY_FOR_WAKEUP bit to be set?
- what causes the bit to be cleared.
- once the bit is set, is it guaranteed to stay set until the ULP wakes the main processor, or can it clear again. If so, is that a fixed timing window, or based on other conditions.
persistence of RTC_CNTL_RDY_FOR_WAKEUP bit
Re: persistence of RTC_CNTL_RDY_FOR_WAKEUP bit
Bump, please.
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Re: persistence of RTC_CNTL_RDY_FOR_WAKEUP bit
Hi @ircrowe,
Previous useful discussion on this topic:
viewtopic.php?t=10028
Additionally discussion at https://github.com/espressif/esp-idf/is ... -627187838 is something that you might find useful as well.
We will try to prioritise documentation updates on our side on this topic.
Thanks.
Entry into sleep mode (either light or deep sleep) causes this bit to be set- what causes the RTC_CNTL_RDY_FOR_WAKEUP bit to be set?
Exit from sleep mode- what causes the bit to be cleared.
No, this bit is not guaranteed to stay set (e.g., multiple wakeup sources configured and system exits sleep mode due to one of them).- once the bit is set, is it guaranteed to stay set until the ULP wakes the main processor, or can it clear again. If so, is that a fixed timing window, or based on other conditions.
Previous useful discussion on this topic:
viewtopic.php?t=10028
Additionally discussion at https://github.com/espressif/esp-idf/is ... -627187838 is something that you might find useful as well.
We will try to prioritise documentation updates on our side on this topic.
Thanks.
Mahavir
https://github.com/mahavirj/
https://github.com/mahavirj/
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