VDD_SDIO, RTC, cache, strap pins

AlexESP32
Posts: 65
Joined: Thu Oct 03, 2019 9:41 am

VDD_SDIO, RTC, cache, strap pins

Postby AlexESP32 » Wed Jan 27, 2021 8:42 pm

Hello guys.

I check the bootloader code of 2. stage bootloader and therefore I have some questions. Maybe some can answer these questions:

1. All of the code starting from the function "call_start_cpu0" is already in RAM via the help of MMU and cache? When will be the next instruction which loads more instructions into the cache?

2. Which flash is inside the ESP32-WROOM? I cannot find the manufacturer / datasheets?

3. If the flash cannot run with 3.3V, do I need therefore the 1.8V - 1.9V of the VDD_SDIO? Why I should change the voltage of 1.8V or 1.9V (in menuconfig), what are the advantages /disadvantages of this change? It is only power consumption?

4. To get the VDD_SDIO config there is the function "rtc_vddsdio_get_config" --> why this topic is in "rtc"? In my opinion rtc is only for real time clock and it is not done for vdd configuration (for example)?

5. What are the strap pins for (MTDI strap pin)?

Thank you very much ;)

Greetings

WiFive
Posts: 3529
Joined: Tue Dec 01, 2015 7:35 am

Re: VDD_SDIO, RTC, cache, strap pins

Postby WiFive » Thu Jan 28, 2021 2:33 am

1. The whole bootloader is running from iram it was copied there by first stage bootloader
2. https://github.com/espressif/esp-idf/tr ... /spi_flash
3. Only for flash chips that have to run at 1.8v spec for example the older wrover modules and d2wd chips, boost voltage is for reliability
4. Rtc subsystem is part of the chip that does these things, that was the chosen name
5. Strapping pins are to configure hardware at boot time for example if efuse is not configured

AlexESP32
Posts: 65
Joined: Thu Oct 03, 2019 9:41 am

Re: VDD_SDIO, RTC, cache, strap pins

Postby AlexESP32 » Thu Jan 28, 2021 7:17 pm

Hello,

Thank you.

1. Okay. So if bootloader is finished, then parts of the application code will be copied into IRAM? How can the MMU load the actual firmware although the MMU doesn't know which code will be executed next?

2. Thank you. In spi_flash_chip_generic.c there is the acutal chip listed: GD25Q127 Am I right?

3. So in actual ESP-WROOM-32 the VDD_SDIO must be 3.3V? The datasheet recommended that

4. Okay. Again the question: Why the VDD_SDIO configuration (a configuration to adjust the voltage of a pin) is in the RTC (real time clock)? I dont understand the correlation of these 2 topics...

5. Ah okay. That makes sense.

Greetings

WiFive
Posts: 3529
Joined: Tue Dec 01, 2015 7:35 am

Re: VDD_SDIO, RTC, cache, strap pins

Postby WiFive » Thu Jan 28, 2021 8:36 pm

1. cache will reload automatically, I don't know the exact implementation i.e. lookahead cache. You can study theory of cache design if you want.
2. I don't think there is a guarantee that all module production runs will have the same flash chip, that is why there is a unified flash API
3. Yes
4. It could have been called "power management, clock, and rtc subsystem" but it was shortened to rtc. Don't lose sleep over it.

Studying the low level details for academic reasons is fine, but mostly just use the SDK!

AlexESP32
Posts: 65
Joined: Thu Oct 03, 2019 9:41 am

Re: VDD_SDIO, RTC, cache, strap pins

Postby AlexESP32 » Fri Jan 29, 2021 7:11 am

Thank you very much :)

1. All right. I think so too about the cache implementation. I have to check this in detail in future.
2. Okay. Then I think I will open the case of the esp32 and will check the vendor of the flash
3. All right.
4. All right.

I used the SDK, now I want check the ESP32 in detail :)

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