SPI timing violation using hardware chip-select

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luca.gamma
Posts: 15
Joined: Tue Apr 19, 2016 8:40 pm
Location: Switzerland

SPI timing violation using hardware chip-select

Postby luca.gamma » Fri Feb 24, 2017 4:58 pm

Configuring the SPI master peripheral (HSPI) I require at least half bit-cycle after transmission before the chip-select becomes inactive. The SPI device interface configuration structure has a member called 'cs_ena_posttrans' which should be set to the number of bit-cycle to wait. Actually setting this member to 0 the CS rise just after the last transmission clock but setting to 1 the timing doesn't change. To add 1 bit-cycle I had to set the value to 2 or 3 to wait for 2 bit-cycles and so on. Is this a bug or is it in some way the desired behaviour?

WiFive
Posts: 3529
Joined: Tue Dec 01, 2015 7:35 am

Re: SPI timing violation using hardware chip-select

Postby WiFive » Fri Feb 24, 2017 9:04 pm

Seems like bug as TRM doesn't say number of cycles minus one but that is what driver uses

ESP_Sprite
Posts: 9766
Joined: Thu Nov 26, 2015 4:08 am

Re: SPI timing violation using hardware chip-select

Postby ESP_Sprite » Sun Feb 26, 2017 7:11 am

Huh, may be my bad. I'll look into it.

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