Suggest rewriting some of the ESP-IDF UART doc

[zliudr]

I've read from the technical manual that there is a shared 1KB memory among the 3 UART controllers for RX and TX fifo buffer. With ESP-IDF uart driver installer, you can provide RX and TX fifo buffer. I want to suggest the author(s) of the document to make clear distinctions between the "hardware" shared FIFO buffer that I think is managed independently from CPU and the "software" buffer that I think is filled by CPU emptying the hardware FIFO RX buffer or dumping to the hardware FIFO TX buffer. As the doc reads now, there is no distinction:

https://docs.espressif.com/projects/esp ... /uart.html

For instance, the uart_read_bytes() says it reads from RX buffer but what if there are m bytes in the hardware buffer and n bytes in the software buffer? Will read returns them all if I ask to read a large enough length?

[WiFive]

Data is copied out of hardware fifo into ringbuffer when ringbuffer is full (threshold) or when frame ends (rx line idle).

[zliudr]

Thanks for clarifying. So there are interrupts and handlers such as FIFO full and RX idle for those? FYI, from my logic analyzer, the stop after each byte is rather short (nothing wrong with being short), compared with what I get from an arduino board's 16U2 that acts as USB/UART adapter. Same baud rate, 16U2's firmware takes almost twice the time to transfer the same data as ESP32 because it has long stops.