Connect external flash

[chromebin]

My hardware designer connected a 4MB 3.3V QSPI flash to the set of pins 17 to 22, with notably CS on GPIO11.

Now what do I do to enable the flash in software?

I tried adjusting the partitions.csv, but apparently the memory isn't recognized. The ESP32-WROOM continues to work with 4MB.

I found old threads relating to this topic, I expected something like:

http://esp-idf.readthedocs.io/en/latest ... l-ram.html

Thanks.

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Just repeating an observation voiced before: 4MB works, but isn't future proof in a world with frequent firmware updates, as is typical in Iot. Some consideration which also lead to a need for more memory are:
- some devices must buffer and relay OTA updates for other devices (ESPNOW)
- need storage for media such as sound samples (ca 1MB)

So a 8MB ESP32 would be the right part for us. As we ramp up we can't invest in a custom order. Thanks for considering.

[WiFive]

https://esp32.com/viewtopic.php?f=17&t=4666

[chromebin]

Thanks Wifive. Again.

The repo referenced, https://github.com/lllucius/esp32_extflash, unfortunately seems to treat the flash as memory accessed through explicit SPI operations, such as erase_range().

I was under the impression the ESP32 was able to access additional memory transparently, as memory, adding to the memory space, the ESP directly executing from it, caching it, etc. That would be a much much superior solution. Hence my request for a configuration recipy, as seems to exist for the PSRAM.

Is my impression wrong?

Note, the memory is connected to native pins, in parallel with the internal flash.

[WiFive]

I'm not sure where you got that impression that multiple flash chips can be used in parallel with cache. Even if possible would at least require a different cs pin. Some people have connected a larger external flash in parallel with different cs but this was with the intention of not using the internal flash.

FYI 8mb and 16mb modules are now available from distributors.

[chromebin]

I'm not sure where you got that impression that multiple flash chips can be used in parallel with cache.

Well they use the same SPI and that SPI supports several CS, so that suggests they use the same "backend". In other words, why treat them differently? Also, the cache *is* used when using the external 4MB PSRAM, so a 2nd flash would be the exception here(!).

FYI 8mb and 16mb modules are now available from distributors.

Thanks. Indeed Mouser has them. My contact was 2-3 months ago, I expected to be updated when available :/

[WiFive]

It would have to be implemented in the mmu and unless the mmu supports partitioning the address space to multiple chips then only 1 flash and 1 ram are supported.

[Oleg Endo]

I ran into a similar question ....
Does the ESP32 MMU/Cache support multiple flash chips on different CS lines? For example have one flash on CS0 for Vaddr(0) area, one RAM for Vaddr(ram) area on CS1 and another flash chip on CS2 for Vaddr(1-3) area, or something like that? Is that possible or not? Unfortunately all those hardware parts are pretty much undocumented ...

Also, what's the size of each R/W (burst) access to the external SPI memories? 1 cache line = 32 bytes?

Can somebody from Espressif please clarify it?

[ESP_igrr]

If you need the 2nd flash chip on a different CS line for storage only, you can use the new spi_flash APIs which support multiple chips (https://docs.espressif.com/projects/esp ... ash-device). Sorry, no example for this yet, will be added soon.

Regarding using different CS lines for different MMU ranges, I'm afraid this isn't possible, at hardware level.

[Oleg Endo]

My idea was indeed to have 2 flash chips on different CS lines to be used by the MMU / Cache, not as explicit SPI storage via SPI commands. Thanks for confirming that this is not possible