Pre/post increment FP load/store instructions.

[peter32]

TL;DR: Can someone confirm that the ESP32 uses postincrement FP load/store.

The Xtensa Instruction Set Architecture reference manual documents a quartet of instructions that load/store a float and update the address register (LSIU, LSXU, SSIU, SSXU). These are useful for stepping through arrays.

I first discovered the existence of these instructions when my attempt to build a esp-idf application generated:

/tmp/ccdeTmSo.s:5633: Error: unknown opcode or format name 'ssiu'

The SSIU instruction word looks like:

Code: Select all

i i i i i i i i 1 1 0 0 s s s s t t t t 0 0 1 1

and the ISA manual states the operation is:

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Vaddr ← AR[s] + (i << 2)
Store32(Vaddr, FR[t])
AR[s] ← Vaddr

Some digging through the binutils sources turned up an instruction SSIP that
was encoded as:

Code: Select all

i i i i i i i i 1 1 0 0 s s s s t t t t 0 0 1 1

(ie, the same as the ISA documented for SSIU)

And some further digging turned up a GCC patch (eg https://marc.info/?l=gcc-patches&m=141315401507078&w=2) that stated "Earlier versions of xtensa FPU used to support preincrement FP load and store instructions (lsiu/ssiu). Recent FPU supports postincrement FP load and store instructions only (lsip/ssip)." The choice between pre-increment and post-increment is a compile-time option controlled by the XCHAL_HAVE_FP_POSTINC option in the core-isa.h file. The ESP32 core-isa.h files I can find (eg Customer ID=11657; Build=0x5fe96, supplied with esp-idf) do not mention XCHAL_HAVE_FP_POSTINC, hence GCC is defaulting to pre-increment mode and generating SSIU/LSIU instructions.

OTOH, some experimental code intended to check the actual behaviour suggests my ESP32-WROVER-B module is actually post-increment mode. Can someone confirm that all ESP32 modules use the post-increment definition.

(I will refrain on commenting on the wisdom of silently changing an opcode from meaning *++x to meaning *x++)

[ESP_Sprite]

As far as I can tell, the pre-increment store (ssiu) is only available on an earlier incarnation of the Xtensa FPU; the ESP32 does not have this and it uses the newer version instead, so LSIP/SSIP are supported operations. These indeed post-increment: "LSIP is a 32-bit load from memory to the floating-point register file with base address register post-increment."

You are right in that we for some reason do not have XCHAL_HAVE_FP_POSTINC set in the overlay; I'm halfway sure this is because the Xtensa tools we used to generate these at that time did not generate this define. It should indeed be set.

Can I ask what code you tried to compile, so we can use this as a testcase? If you don't want to disclose it publicly, you can also mail it to jeroen at espressif dot com.

[ESP_Sprite]

Ah, a colleague kindly informed me that this is a known issue, see e.g. this bug. If you want, you can use the gcc 8.2 toolchain as linked in that issue; it should fix the issue.