PSRAM toolchain patch build error

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Ritesh
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Re: PSRAM toolchain patch build error

Postby Ritesh » Mon Sep 11, 2017 8:42 am

Hi Espressif Systems Developer,

Would you please confirm that PSRAM supported branch changes have been ported and included into current master branch or not?

If not then can you please tell me what is your planning to merge into master branch or any stable branch in future?
Regards,
Ritesh Prajapati
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loboris
Posts: 514
Joined: Wed Dec 21, 2016 7:40 pm

Re: PSRAM toolchain patch build error

Postby loboris » Mon Sep 11, 2017 8:51 am

rahul.b.patel wrote:Hi Loboris,
Yes of course simple malloc is not supported yet, but we tested it using pvPortMallocCaps(size, MALLOC_CAP_SPIRAM).
While using buffer = pvPortMallocCaps(10, MALLOC_CAP_SPIRAM), we got "buffer" address as 0x3f800008.
We tested it with 40MHz speed only. This works with feature/psram_malloc branch but not with current master branch.
Only SPI RAM access method (Integrate RAM into ESP32 memory map) psram access method is available at the moment.
Try with this code, it works with esp-idf master branch, (you still have to use psram toolchain):

Code: Select all

#include <stdio.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_system.h"
#include "esp_spi_flash.h"
#include <time.h>
#include <stdio.h>
#include <string.h>

#define BUF_SIZE 2*1024*1024
//----------------
void spiram_test()
{
    uint32_t t1, t2, t3, t4;
    uint8_t *buf1;
    uint8_t *buf2;
    uint8_t *pbuf1;
    uint8_t *pbuf2;
    uint8_t testb;
    uint32_t idx;
    int pass = 0;
    while (1)  {  
        vTaskDelay(1000 / portTICK_PERIOD_MS);
        pass++;
        if (pass > 10) break;

        if (pass % 2) testb = 0xA5;
        else testb = 0x5A;
        
        printf("\n======= PSRAM Test (%u bytes block) pass %d =======\n", BUF_SIZE, pass);

        buf1 = (uint8_t *)0x3f800000;
        buf2 = (uint8_t *)0x3f800000+BUF_SIZE;

        t1 = clock();
        memset(buf1, testb, BUF_SIZE);
        memset(buf2, testb, BUF_SIZE);
        t1 = clock() - t1;
        
        t2 = clock();
        int res = memcmp(buf1, buf2, BUF_SIZE);
        t2 = clock() - t2;
 
        pbuf1 = buf1;
        pbuf2 = buf2;
        t4 = clock();
        for (idx=0; idx < BUF_SIZE; idx++) {
            *pbuf1++ = testb;
        }
        for (idx=0; idx < BUF_SIZE; idx++) {
            *pbuf2++ = testb;
        }
        t4 = clock() - t4;

        pbuf1 = buf1;
        pbuf2 = buf2;
        t3 = clock();
        for (idx=0; idx < BUF_SIZE; idx++) {
            if (*pbuf1 != *pbuf2) break;
            pbuf1++;
            pbuf2++;
        }
        t3 = clock() - t3;
        
        float bs = ((1000.0 / (float)t1 * (float)(BUF_SIZE*2))) / 1048576.0;
        printf("               memset time: %u ms; %f MB/sec\n", t1, bs);
        bs = ((1000.0 / (float)t2 * (float)(BUF_SIZE))) / 1048576.0;
        if (res == 0) printf("               memcmp time: %u ms; %f Mcompares/sec\n", t2, bs);
        else printf("               memcmp time: %u ms; FAILED (%d)\n", t2, res);

        bs = ((1000.0 / (float)t4 * (float)(BUF_SIZE*2))) / 1048576.0;
        printf("   Memory set in loop time: %u ms; %f MB/sec\n", t4, bs);
        bs = ((1000.0 / (float)t3 * (float)(BUF_SIZE))) / 1048576.0;
        printf("  Compare in loop time idx: %u ms; %f Mcompares/sec (%u of %u OK)\n", t3, bs, idx, BUF_SIZE);
        printf("      1st 16 bytes of buf1: ");
        for (idx=0; idx<16;idx++) {
            printf("%02X ", buf1[idx]);
        }
        printf("\n");
        printf("      1st 16 bytes of buf2: ");
        for (idx=0; idx<16;idx++) {
            printf("%02X ", buf2[idx]);
        }
        printf("\n");
    }
}

//=============
void app_main()
{
    vTaskDelay(100 / portTICK_PERIOD_MS);
    printf("\nSPIRAM test!\n");

    /* Print chip information */
    esp_chip_info_t chip_info;
    esp_chip_info(&chip_info);
    printf("ESP32 with %d CPU cores, silicon rev %d, ", chip_info.cores, chip_info.revision);
    printf("%dMB %s flash\n\n", spi_flash_get_chip_size() / (1024 * 1024),
            (chip_info.features & CHIP_FEATURE_EMB_FLASH) ? "embedded" : "external");
#ifdef CONFIG_FREERTOS_UNICORE
    printf("FreeRTOS RUNNING ON FIRST CORE\n");
#else
    printf("FreeRTOS RUNNING ON BOTH CORES\n");
#endif

    spiram_test();
}
Log:

Code: Select all

MONITOR
--- idf_monitor on /dev/ttyUSB1 115200 ---
--- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H ---
ets Jun  8 2016 00:22:57

rst:0x1 (POWERON_RESET),boot:0x3e (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0010,len:4
load:0x3fff0014,len:5400
load:0x40078000,len:0
ho 12 tail 0 room 4
load:0x40078000,len:13176
entry 0x40078fe8
I (46) boot: ESP-IDF v3.0-dev-606-g050ae50e 2nd stage bootloader
I (46) boot: compile time 10:43:07
I (89) boot: Enabling RNG early entropy source...
I (89) boot: SPI Speed      : 40MHz
I (89) boot: SPI Mode       : DIO
I (97) boot: SPI Flash Size : 4MB
I (110) boot: Partition Table:
I (121) boot: ## Label            Usage          Type ST Offset   Length
I (144) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (167) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (190) boot:  2 factory          factory app      00 00 00010000 00100000
I (214) boot: End of partition table
I (227) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f400020 size=0x081c8 ( 33224) map
I (290) esp_image: segment 1: paddr=0x000181f0 vaddr=0x3ffb0000 size=0x021b0 (  8624) load
I (301) esp_image: segment 2: paddr=0x0001a3a8 vaddr=0x40080000 size=0x00400 (  1024) load
0x40080000: _iram_start at /home/LoBo2_Razno/ESP32/esp-idf/components/freertos/./xtensa_vectors.S:1675

I (317) esp_image: segment 3: paddr=0x0001a7b0 vaddr=0x40080400 size=0x05860 ( 22624) load
I (372) esp_image: segment 4: paddr=0x00020018 vaddr=0x400d0018 size=0x14288 ( 82568) map
0x400d0018: _stext at ??:?

I (461) esp_image: segment 5: paddr=0x000342a8 vaddr=0x40085c60 size=0x044cc ( 17612) load
0x40085c60: xQueueReceiveFromISR at /home/LoBo2_Razno/ESP32/esp-idf/components/freertos/./queue.c:2034

I (484) esp_image: segment 6: paddr=0x0003877c vaddr=0x400c0000 size=0x00000 (     0) load
I (505) boot: Loaded app from partition at offset 0x10000
I (505) boot: Disabling RNG early entropy source...
I (522) spiram: SPI RAM mode: flash 40m sram 40m
I (533) spiram: PSRAM initialized, cache is in low/high (2-core) mode.
I (556) cpu_start: Pro cpu up.
I (567) cpu_start: Starting app cpu, entry point is 0x40080fa8
0x40080fa8: call_start_cpu1 at /home/LoBo2_Razno/ESP32/esp-idf/components/esp32/./cpu_start.c:219

I (0) cpu_start: App cpu up.
I (3334) spiram: SPI SRAM memory test OK
I (3336) heap_init: Initializing. RAM available for dynamic allocation:
I (3336) heap_init: At 3FFAE2A0 len 00001D60 (7 KiB): DRAM
I (3355) heap_init: At 3FFB29D0 len 0002D630 (181 KiB): DRAM
I (3374) heap_init: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
I (3394) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (3414) heap_init: At 4008A12C len 00015ED4 (87 KiB): IRAM
I (3433) cpu_start: Pro cpu start user code
I (3495) cpu_start: Starting scheduler on PRO CPU.
I (2916) cpu_start: Starting scheduler on APP CPU.

SPIRAM test!
ESP32 with 2 CPU cores, silicon rev 1, 4MB external flash

FreeRTOS RUNNING ON BOTH CORES

======= PSRAM Test (2097152 bytes block) pass 1 =======
               memset time: 550 ms; 7.272727 MB/sec
               memcmp time: 480 ms; 4.166667 Mcompares/sec
   Memory set in loop time: 1000 ms; 4.000000 MB/sec
  Compare in loop time idx: 500 ms; 4.000000 Mcompares/sec (2097152 of 2097152 OK)
      1st 16 bytes of buf1: A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 
      1st 16 bytes of buf2: A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 

======= PSRAM Test (2097152 bytes block) pass 2 =======
               memset time: 550 ms; 7.272727 MB/sec
               memcmp time: 480 ms; 4.166667 Mcompares/sec
   Memory set in loop time: 1000 ms; 4.000000 MB/sec
  Compare in loop time idx: 500 ms; 4.000000 Mcompares/sec (2097152 of 2097152 OK)
      1st 16 bytes of buf1: 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 
      1st 16 bytes of buf2: 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A
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ESP_Sprite
Posts: 9761
Joined: Thu Nov 26, 2015 4:08 am

Re: PSRAM toolchain patch build error

Postby ESP_Sprite » Mon Sep 11, 2017 9:08 am

Confirm what Loboris says. We're slowly integrating the changes in the PSRAM branch into esp-idf master in order to fully release them with esp-idf v3.0. It will be a piece-by-piece process, however.
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Ritesh
Posts: 1383
Joined: Tue Sep 06, 2016 9:37 am
Location: India
Contact:
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Re: PSRAM toolchain patch build error

Postby Ritesh » Mon Sep 11, 2017 9:13 am

ESP_Sprite wrote:Confirm what Loboris says. We're slowly integrating the changes in the PSRAM branch into esp-idf master in order to fully release them with esp-idf v3.0. It will be a piece-by-piece process, however.
Thanks for quick Reply.

I understood it and will wait for that. Let us know once all changes have been included into ESP32 IDF 3.0 Branch for all PSRAM related changes.
Regards,
Ritesh Prajapati
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Ritesh
Posts: 1383
Joined: Tue Sep 06, 2016 9:37 am
Location: India
Contact:
Contact Ritesh

Re: PSRAM toolchain patch build error

Postby Ritesh » Mon Sep 11, 2017 9:15 am

loboris wrote:
rahul.b.patel wrote:Hi Loboris,
Yes of course simple malloc is not supported yet, but we tested it using pvPortMallocCaps(size, MALLOC_CAP_SPIRAM).
While using buffer = pvPortMallocCaps(10, MALLOC_CAP_SPIRAM), we got "buffer" address as 0x3f800008.
We tested it with 40MHz speed only. This works with feature/psram_malloc branch but not with current master branch.
Only SPI RAM access method (Integrate RAM into ESP32 memory map) psram access method is available at the moment.
Try with this code, it works with esp-idf master branch, (you still have to use psram toolchain):

Code: Select all

#include <stdio.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_system.h"
#include "esp_spi_flash.h"
#include <time.h>
#include <stdio.h>
#include <string.h>

#define BUF_SIZE 2*1024*1024
//----------------
void spiram_test()
{
    uint32_t t1, t2, t3, t4;
    uint8_t *buf1;
    uint8_t *buf2;
    uint8_t *pbuf1;
    uint8_t *pbuf2;
    uint8_t testb;
    uint32_t idx;
    int pass = 0;
    while (1)  {  
        vTaskDelay(1000 / portTICK_PERIOD_MS);
        pass++;
        if (pass > 10) break;

        if (pass % 2) testb = 0xA5;
        else testb = 0x5A;
        
        printf("\n======= PSRAM Test (%u bytes block) pass %d =======\n", BUF_SIZE, pass);

        buf1 = (uint8_t *)0x3f800000;
        buf2 = (uint8_t *)0x3f800000+BUF_SIZE;

        t1 = clock();
        memset(buf1, testb, BUF_SIZE);
        memset(buf2, testb, BUF_SIZE);
        t1 = clock() - t1;
        
        t2 = clock();
        int res = memcmp(buf1, buf2, BUF_SIZE);
        t2 = clock() - t2;
 
        pbuf1 = buf1;
        pbuf2 = buf2;
        t4 = clock();
        for (idx=0; idx < BUF_SIZE; idx++) {
            *pbuf1++ = testb;
        }
        for (idx=0; idx < BUF_SIZE; idx++) {
            *pbuf2++ = testb;
        }
        t4 = clock() - t4;

        pbuf1 = buf1;
        pbuf2 = buf2;
        t3 = clock();
        for (idx=0; idx < BUF_SIZE; idx++) {
            if (*pbuf1 != *pbuf2) break;
            pbuf1++;
            pbuf2++;
        }
        t3 = clock() - t3;
        
        float bs = ((1000.0 / (float)t1 * (float)(BUF_SIZE*2))) / 1048576.0;
        printf("               memset time: %u ms; %f MB/sec\n", t1, bs);
        bs = ((1000.0 / (float)t2 * (float)(BUF_SIZE))) / 1048576.0;
        if (res == 0) printf("               memcmp time: %u ms; %f Mcompares/sec\n", t2, bs);
        else printf("               memcmp time: %u ms; FAILED (%d)\n", t2, res);

        bs = ((1000.0 / (float)t4 * (float)(BUF_SIZE*2))) / 1048576.0;
        printf("   Memory set in loop time: %u ms; %f MB/sec\n", t4, bs);
        bs = ((1000.0 / (float)t3 * (float)(BUF_SIZE))) / 1048576.0;
        printf("  Compare in loop time idx: %u ms; %f Mcompares/sec (%u of %u OK)\n", t3, bs, idx, BUF_SIZE);
        printf("      1st 16 bytes of buf1: ");
        for (idx=0; idx<16;idx++) {
            printf("%02X ", buf1[idx]);
        }
        printf("\n");
        printf("      1st 16 bytes of buf2: ");
        for (idx=0; idx<16;idx++) {
            printf("%02X ", buf2[idx]);
        }
        printf("\n");
    }
}

//=============
void app_main()
{
    vTaskDelay(100 / portTICK_PERIOD_MS);
    printf("\nSPIRAM test!\n");

    /* Print chip information */
    esp_chip_info_t chip_info;
    esp_chip_info(&chip_info);
    printf("ESP32 with %d CPU cores, silicon rev %d, ", chip_info.cores, chip_info.revision);
    printf("%dMB %s flash\n\n", spi_flash_get_chip_size() / (1024 * 1024),
            (chip_info.features & CHIP_FEATURE_EMB_FLASH) ? "embedded" : "external");
#ifdef CONFIG_FREERTOS_UNICORE
    printf("FreeRTOS RUNNING ON FIRST CORE\n");
#else
    printf("FreeRTOS RUNNING ON BOTH CORES\n");
#endif

    spiram_test();
}
Log:

Code: Select all

MONITOR
--- idf_monitor on /dev/ttyUSB1 115200 ---
--- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H ---
ets Jun  8 2016 00:22:57

rst:0x1 (POWERON_RESET),boot:0x3e (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0010,len:4
load:0x3fff0014,len:5400
load:0x40078000,len:0
ho 12 tail 0 room 4
load:0x40078000,len:13176
entry 0x40078fe8
I (46) boot: ESP-IDF v3.0-dev-606-g050ae50e 2nd stage bootloader
I (46) boot: compile time 10:43:07
I (89) boot: Enabling RNG early entropy source...
I (89) boot: SPI Speed      : 40MHz
I (89) boot: SPI Mode       : DIO
I (97) boot: SPI Flash Size : 4MB
I (110) boot: Partition Table:
I (121) boot: ## Label            Usage          Type ST Offset   Length
I (144) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (167) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (190) boot:  2 factory          factory app      00 00 00010000 00100000
I (214) boot: End of partition table
I (227) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f400020 size=0x081c8 ( 33224) map
I (290) esp_image: segment 1: paddr=0x000181f0 vaddr=0x3ffb0000 size=0x021b0 (  8624) load
I (301) esp_image: segment 2: paddr=0x0001a3a8 vaddr=0x40080000 size=0x00400 (  1024) load
0x40080000: _iram_start at /home/LoBo2_Razno/ESP32/esp-idf/components/freertos/./xtensa_vectors.S:1675

I (317) esp_image: segment 3: paddr=0x0001a7b0 vaddr=0x40080400 size=0x05860 ( 22624) load
I (372) esp_image: segment 4: paddr=0x00020018 vaddr=0x400d0018 size=0x14288 ( 82568) map
0x400d0018: _stext at ??:?

I (461) esp_image: segment 5: paddr=0x000342a8 vaddr=0x40085c60 size=0x044cc ( 17612) load
0x40085c60: xQueueReceiveFromISR at /home/LoBo2_Razno/ESP32/esp-idf/components/freertos/./queue.c:2034

I (484) esp_image: segment 6: paddr=0x0003877c vaddr=0x400c0000 size=0x00000 (     0) load
I (505) boot: Loaded app from partition at offset 0x10000
I (505) boot: Disabling RNG early entropy source...
I (522) spiram: SPI RAM mode: flash 40m sram 40m
I (533) spiram: PSRAM initialized, cache is in low/high (2-core) mode.
I (556) cpu_start: Pro cpu up.
I (567) cpu_start: Starting app cpu, entry point is 0x40080fa8
0x40080fa8: call_start_cpu1 at /home/LoBo2_Razno/ESP32/esp-idf/components/esp32/./cpu_start.c:219

I (0) cpu_start: App cpu up.
I (3334) spiram: SPI SRAM memory test OK
I (3336) heap_init: Initializing. RAM available for dynamic allocation:
I (3336) heap_init: At 3FFAE2A0 len 00001D60 (7 KiB): DRAM
I (3355) heap_init: At 3FFB29D0 len 0002D630 (181 KiB): DRAM
I (3374) heap_init: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
I (3394) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (3414) heap_init: At 4008A12C len 00015ED4 (87 KiB): IRAM
I (3433) cpu_start: Pro cpu start user code
I (3495) cpu_start: Starting scheduler on PRO CPU.
I (2916) cpu_start: Starting scheduler on APP CPU.

SPIRAM test!
ESP32 with 2 CPU cores, silicon rev 1, 4MB external flash

FreeRTOS RUNNING ON BOTH CORES

======= PSRAM Test (2097152 bytes block) pass 1 =======
               memset time: 550 ms; 7.272727 MB/sec
               memcmp time: 480 ms; 4.166667 Mcompares/sec
   Memory set in loop time: 1000 ms; 4.000000 MB/sec
  Compare in loop time idx: 500 ms; 4.000000 Mcompares/sec (2097152 of 2097152 OK)
      1st 16 bytes of buf1: A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 
      1st 16 bytes of buf2: A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 

======= PSRAM Test (2097152 bytes block) pass 2 =======
               memset time: 550 ms; 7.272727 MB/sec
               memcmp time: 480 ms; 4.166667 Mcompares/sec
   Memory set in loop time: 1000 ms; 4.000000 MB/sec
  Compare in loop time idx: 500 ms; 4.000000 Mcompares/sec (2097152 of 2097152 OK)
      1st 16 bytes of buf1: 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 
      1st 16 bytes of buf2: 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A
Hi Loboris,

Ok. We will try that example on ESP32 IDF Master branch with PSRAM supported Toolchain and will get back to you if any issue while using that example.
Regards,
Ritesh Prajapati
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User avatar
rudi ;-)
Posts: 1729
Joined: Fri Nov 13, 2015 3:25 pm

Re: PSRAM toolchain patch build error

Postby rudi ;-) » Wed Nov 08, 2017 3:59 pm

ESP_Sprite wrote:Confirm what Loboris says. We're slowly integrating the changes in the PSRAM branch into esp-idf master in order to fully release them with esp-idf v3.0. It will be a piece-by-piece process, however.
hi jeroen,
can it be that the esp32-doom does not run with the actually master?

txs
best wishes
rudi ;-)
-------------------------------------
love it, change it or leave it.
-------------------------------------
問候飛出去的朋友遍全球魯迪
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