High Bandwidth Applications - Is there any advantage to using multiple SPI busses?

[fermienrico]

I have an SPI peripheral project with up to 10 SPI devices using the same Chip-select (CS) pin.

Is there any advantage to split them between two SPI busses, say, 5 devices connected to VSPI and 5 devices connected to HSPI in terms of overall processing power/bandwidth?

These devices are LCD screens and the framerate is directly related to the frequency of transfer. For example, I can change the SPI frequency from 4 MHz to 8Mhz and the framerate doubles. What, if any, would be the advantage of using HSPI and VSPI SPI busses simultaneously? Can they be used in parallel - VSPI dedicated to one core and HSPI dedicated to another FreeRTOS task on another core?

Thank you,
Fermi

[johnabel]

So, do you have a number of SPI devices all of them sharing the same CS\ signal?
How do you make sure they don't clash to drive the MOSI line?
The goodness of SPI is you can have as many devices as you need as long as you enable them one by one.
One of the reasons I would split SPI devices into different ports is to use different settings (clock, mode, etc) and not having to change them before every communication.
Having multiple SPI ports would only speed up things if you use DMA, otherwise is about the same polling devices in one port or more than one.
SPI implementations in microcontrollers have a limit to the number of devices (8 is typical), that could be another reason to split ten of them in two ports.