- rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
- configsip: 0, SPIWP:0xee
- clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
- mode:DIO, clock div:2
- load:0x3fff0030,len:7176
- load:0x40078000,len:15564
- ho 0 tail 12 room 4
- load:0x40080400,len:4
- --- 0x40080400: _init at ??:?
- load:0x40080404,len:3904
- entry 0x40080640
- I (31) boot: ESP-IDF v5.3.1-244-g4d0db7045d 2nd stage bootloader
- I (31) boot: compile time Sep 23 2024 22:36:41
- I (33) boot: Multicore bootloader
- I (37) boot: chip revision: v3.1
- I (41) boot.esp32: SPI Speed : 40MHz
- I (45) boot.esp32: SPI Mode : DIO
- I (50) boot.esp32: SPI Flash Size : 2MB
- I (54) boot: Enabling RNG early entropy source...
- I (60) boot: Partition Table:
- I (63) boot: ## Label Usage Type ST Offset Length
- I (71) boot: 0 nvs WiFi data 01 02 00009000 00006000
- I (78) boot: 1 phy_init RF data 01 01 0000f000 00001000
- I (86) boot: 2 factory factory app 00 00 00010000 00100000
- I (93) boot: End of partition table
- I (97) esp_image: segment 0: paddr=00010020 vaddr=3f400020 size=0abbch ( 43964) map
- I (121) esp_image: segment 1: paddr=0001abe4 vaddr=3ffb0000 size=02348h ( 9032) load
- I (124) esp_image: segment 2: paddr=0001cf34 vaddr=40080000 size=030e4h ( 12516) load
- I (132) esp_image: segment 3: paddr=00020020 vaddr=400d0020 size=16e7ch ( 93820) map
- I (167) esp_image: segment 4: paddr=00036ea4 vaddr=400830e4 size=09e40h ( 40512) load
- I (190) boot: Loaded app from partition at offset 0x10000
- I (190) boot: Disabling RNG early entropy source...
- I (202) cpu_start: Multicore app
- I (211) cpu_start: Pro cpu start user code
- I (211) cpu_start: cpu freq: 160000000 Hz
- I (211) app_init: Application information:
- I (214) app_init: Project name: hth-test-stuff
- I (219) app_init: App version: 863dd75-dirty
- I (224) app_init: Compile time: Sep 23 2024 22:36:20
- I (230) app_init: ELF file SHA256: c12088eff...
- I (236) app_init: ESP-IDF: v5.3.1-244-g4d0db7045d
- I (242) efuse_init: Min chip rev: v0.0
- I (247) efuse_init: Max chip rev: v3.99
- I (252) efuse_init: Chip rev: v3.1
- I (257) heap_init: Initializing. RAM available for dynamic allocation:
- I (264) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
- I (270) heap_init: At 3FFB2C10 len 0002D3F0 (180 KiB): DRAM
- I (276) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
- I (282) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
- I (289) heap_init: At 4008CF24 len 000130DC (76 KiB): IRAM
- I (296) spi_flash: detected chip: generic
- I (300) spi_flash: flash io: dio
- W (303) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
- I (317) main_task: Started on CPU0
- I (327) main_task: Calling app_main()
- start of task
- D (327) i2c.common: new bus(0) at 0x3ffaff70
- I (327) gpio: GPIO[21]| InputEn: 1| OutputEn: 1| OpenDrain: 1| Pullup: 1| Pulldown: 0| Intr:0
- I (337) gpio: GPIO[22]| InputEn: 1| OutputEn: 1| OpenDrain: 1| Pullup: 1| Pulldown: 0| Intr:0
- D (347) i2c.common: bus clock source frequency: 80000000hz
- W (347) i2c.master: Please note i2c asynchronous is only used for specific scenario currently. It's experimental for other users because user cannot get bus error from API. And It's not compatible with ``i2c_master_probe``. If user makes sure there won't be any error on bus and tested with no problem, this message can be ignored.
- bus: ESP_OK
- device: ESP_OK
- led pulse width set
- sampling rate set
- Writing to register 0x0A with data 0x11
- ADC resolution set successfully
- adc resolution set
- led current 1 set
- led current 2 set
- led mode set
- fifo configured
- done configuration
- wr_ptr: 23, rd_ptr: 5
- 122032 122026 122140 122033 122066 122126 122066 122036 122048 122051 122161 122045 122269 122059 122058 122180 122226 122011
- polling_num: 1
- wr_ptr: 26, rd_ptr: 22
- 122075 122157 122177 122228
- polling_num: 2
- wr_ptr: 31, rd_ptr: 26
- 122146 122042 122076 122039 122039
- polling_num: 3
- Guru Meditation Error: Core 0 panic'ed (LoadProhibited). Exception was unhandled.
- Core 0 register dump:
- PC : 0x400da203 PS : 0x00060c30 A0 : 0x800d6278 A1 : 0x3ffb3df0
- --- 0x400da203: i2c_master_transmit at C:/Users/benja/esp/v5.3/esp-idf/components/esp_driver_i2c/i2c_master.c:1073
- A2 : 0x3ffb9258 A3 : 0x3ffb3e50 A4 : 0x00000001 A5 : 0xffffffff
- A6 : 0x3ffb3d50 A7 : 0xff000000 A8 : 0x00000000 A9 : 0x00001800
- A10 : 0x00000800 A11 : 0x00000000 A12 : 0x00000030 A13 : 0x3ffb3e30
- A14 : 0x0000021a A15 : 0x00000003 SAR : 0x00000004 EXCCAUSE: 0x0000001c
- EXCVADDR: 0x000000a1 LBEG : 0x4000c46c LEND : 0x4000c477 LCOUNT : 0x00000000
- --- 0x4000c46c: memset in ROM
- 0x4000c477: memset in ROM
- Backtrace: 0x400da200:0x3ffb3df0 0x400d6275:0x3ffb3e50 0x400d6504:0x3ffb3e80 0x400d6671:0x3ffb3eb0 0x400e63e9:0x3ffb3f10 0x40086335:0x3ffb3f30
- --- 0x400da200: i2c_master_transmit at C:/Users/benja/esp/v5.3/esp-idf/components/esp_driver_i2c/i2c_master.c:1067
- 0x400d6275: max30102_read at C:/vscode-esp32-workspace/hth-test-stuff/main/main.c:61
- 0x400d6504: max30102_read_fifo at C:/vscode-esp32-workspace/hth-test-stuff/main/main.c:221
- 0x400d6671: app_main at C:/vscode-esp32-workspace/hth-test-stuff/main/main.c:49
- 0x400e63e9: main_task at C:/Users/benja/esp/v5.3/esp-idf/components/freertos/app_startup.c:208
- 0x40086335: vPortTaskWrapper at C:/Users/benja/esp/v5.3/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c:134
I've spent several days trying to fix a LoadProhibited error to no avail. I wrote two functions, max30102_read and max30102_read_fifo that use i2c_master API's to read/write. I created a global variable polling_num for debugging purposes. When polling_num reaches 2, the task hangs and the watchdog timer reboots the system. When I disabled the watchdog timer, polling_num goes to 3 then a LoadProhibited error occurs.
Would greatly appreciate help.
- void max30102_read_fifo(i2c_master_dev_handle_t *dev_handle)
- {
- // First transaction: Get the FIFO_WR_PTR
- uint8_t wr_ptr = 0, rd_ptr = 0;
- max30102_read(dev_handle, MAX30102_FIFO_RD_PTR, &rd_ptr, 1);
- max30102_read(dev_handle, MAX30102_FIFO_WR_PTR, &wr_ptr, 1);
- vTaskDelay(pdMS_TO_TICKS(100));
- int8_t num_samples;
- printf("wr_ptr: %d, rd_ptr: %d\n", wr_ptr, rd_ptr);
- num_samples = (int8_t)wr_ptr - (int8_t)rd_ptr;
- if (num_samples < 1)
- {
- num_samples += 32;
- }
- // Second transaction: Read NUM_SAMPLES_TO_READ samples from the FIFO
- for (int8_t i = 0; i < num_samples; i++)
- {
- uint8_t sample[6];
- max30102_read(dev_handle, MAX30102_FIFO_DATA, sample, 6);
- uint32_t ir_sample = ((uint32_t)(sample[0] << 16) | (uint32_t)(sample[1] << 8) | (uint32_t)(sample[2])) & 0x3ffff;
- uint32_t red_sample = ((uint32_t)(sample[3] << 16) | (uint32_t)(sample[4] << 8) | (uint32_t)(sample[5])) & 0x3ffff;
- printf("%ld ", ir_sample);
- }
- printf("\n");
- }
- esp_err_t max30102_read(i2c_master_dev_handle_t *dev_handle, uint8_t reg, uint8_t *buf, uint16_t buflen)
- {
- vTaskDelay(pdMS_TO_TICKS(10));
- uint8_t reg_addr = reg;
- // Transmit the register address over I2C
- esp_err_t res = i2c_master_transmit(*dev_handle, ®_addr, 1, -1);
- if (res != ESP_OK) {
- printf("I2C write error: %s\n", esp_err_to_name(res));
- return res;
- }
- // Receive data from the I2C device
- res = i2c_master_receive(*dev_handle, buf, buflen, -1);
- res = ESP_OK;
- if (res != ESP_OK) {
- printf("I2C read error: %s\n", esp_err_to_name(res));
- }
- vTaskDelay(pdMS_TO_TICKS(10));
- return res;
- }