I'm having intermittent LAN8270 connectivity problems where ESP32 MAC -> LAN8720 PHY Fails.
When checking MDIO I see the read request, but no reply from LAN8720 PHY -> ESP32 MAC
When checking MDC, I see the time between each clock cycle to be 320ns = 3MHz.
The MDC Standard is minimum period 400ns or 2.5MHz
I think the MDC Period is too short (MDC frequency too high) making the LAN8270 PHY miss the read sometimes.
Checking MIICSRCLK
This field selects the APB clock frequency. It has the following two values. Other values are reserved.
• 4’b0000: The APB clock frequency is 80 MHz. The MDC clock frequency is APB_CLK/42.
• 4’b0011: The APB clock frequency is 40 MHz. The MDC clock frequency is APB_CLK/26. (R/W)
Adjusting CPU Speed between 80/160/240MHz has no effect on the MDC Speed.
WiFi/BT requires APB @ 80MHz and I have no wifi problems
Can we think of any reason why MDC period is under 400ns?
I just figured out that 80000000/3000000 = 26. Maybe MIICSRCLK is incorrectly set to /26 instead of /42.
To fix this the divider must be updated.
Might just be an old esp-idf problem:
esp_eth_smi_write() {
...
Before: REG_WRITE(EMAC_GMIIADDR_REG, 0x1 | ((reg_num & 0x1f) << 6) | ((phy_num & 0x1f) << 11) | (0x3 << 2));
After: REG_WRITE(EMAC_GMIIADDR_REG, 0x1 | ((reg_num & 0x1f) << 6) | ((phy_num & 0x1f) << 11) | (0x0 << 2));
}