esp32-camera: understanding the interrupts

[Kikiki]

Hi, I'm trying to figure out when those interrupts (DMA, ETS_LCD_CAM_INTR_SOURCE) occur exactly
here is a snippet from https://github.com/espressif/esp32-came ... cam.c#L400

Code: Select all

esp_err_t ll_cam_init_isr(cam_obj_t *cam)
{
	esp_err_t ret = ESP_OK;
    ret = esp_intr_alloc_intrstatus(gdma_periph_signals.groups[0].pairs[cam->dma_num].rx_irq_id,
                                     ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_SHARED | CAMERA_ISR_IRAM_FLAG,
                                     (uint32_t)&GDMA.channel[cam->dma_num].in.int_st, GDMA_IN_SUC_EOF_CH0_INT_ST_M,
                                     ll_cam_dma_isr, cam, &cam->dma_intr_handle);
    if (ret != ESP_OK) {
        ESP_LOGE(TAG, "DMA interrupt allocation of camera failed");
		return ret;
	}

    ret = esp_intr_alloc_intrstatus(ETS_LCD_CAM_INTR_SOURCE,
                                     ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_SHARED | CAMERA_ISR_IRAM_FLAG,
                                     (uint32_t)&LCD_CAM.lc_dma_int_st.val, LCD_CAM_CAM_VSYNC_INT_ST_M,
                                     ll_cam_vsync_isr, cam, &cam->cam_intr_handle);
	if (ret != ESP_OK) {
        ESP_LOGE(TAG, "LCD_CAM interrupt allocation of camera failed");
		return ret;
	}
    return ESP_OK;
}

My guess is that ETS_LCD_CAM_INTR_SOURCE occur before capturing a frame and the dma occurs after the frame dma transfer copied?
Also how the dma knows when and where to copy the frame data from? I didn't find the code of that
Thanks.

[Yuricsson]

Hi,

I had a lot of work with S3 camera module, I needed to read DVP data from AR0135 image sensor in various window sizes. The reference manual has very small amount of information.

Finally you can receive two interrupts from CAM module and one useful interrupt from GDMA - GDMA_IN_SUC_EOF_CHn_INT. GDMA_IN_DONE_CHn_INT is not an interesting one

1) LCD_CAM_CAM_HS_INT triggered when CAM module had received number of _lines_ greater or equal (???) than LCD_CAM_CAM_LINE_INT_NUM + 1. This value is limited by 64, so I didn't liked to receive this interrupt every 64 lines.
2) LCD_CAM_CAM_VSYNC_INT triggered when CAM module had received VSYNC signal. It means that this interrupt triggered at the start of frame. Not very useful.
3) Most interesting one - GDMA_IN_SUC_EOF_CHn_INT. It comes from GDMA module. CAM module can send in_suc_eof trigger to GDMA channel in two cases:
A) when it detects end of the frame (for example, falling edge of VSYNC if you use positive VSYNC polarity).
B) when it had received LCD_CAM_CAM_REC_DATA_BYTELEN+1 total bytes since start of frame.
Case "B" again is not interesting because LCD_CAM_CAM_REC_DATA_BYTELEN is limited by 0xffff, so we can only receive 64K of data. Too small.
Case "A" can be selected by setting LCD_CAM_CAM_VS_EOF_EN bit in LCD_CAM_CAM_CTRL_REG register. Reference manual tells so. BUT I was unable to receive this interrupt! I have tried many ways of configuring CAM module and GDMA channel - no result.

The only solution that I found is to use GPIO falling edge interrupt from VSYNC pin. It really works. I do not configure any GDMA or CAM interrupts. I use camera in snapshot(trigger) mode, SYSCLK/PIXCLK at 72MHz, LINE_VALID (DE) and FRAME_VALID (VSYNC) lines with positive polarity.

Sincerely yours,
Yuri