esp32s3 parallel display config errors

[muzgog]

Hey everyone, I have been working with the esp32s3 Parallel TFT w/ touch 3.5 for about a month now. I know the device works because I used https://github.com/sukesh-ak/ESP32-TUX and got it up and running and made my own little demo using it. I am trying to create a custom board so I can use it for squareline but I am running into some issues. I am using the ili9488 lcd driver on an intel i8080 bus with the ft5x06 touch driver and sending it all through the esp_lvgl_port. Attached below is the code. I have narrowed the issue down to pclk_hz(pixel clock for i80 config),max_transfer_bytes( for the i80 bus), and possibly buffer_size (for the display config for the lvgl_port). Attached below is also the output on the screen I am getting. It is somewhat similar to what I want but has random bars appearing throughout the display, is horribly pixelated, and looks like static TV. All of these variables mentioned above are in my esp32_s3.c file under bsp_display_lcd_init() method. The image should be a white background with a lvgl keyboard, spinning wheel, and slider. I have also attached the main function just in case it is needed to understand the logic. The esp32_s3.h file is where my pins are configured, and from everything I have found, including using the datasheet, they are correct. Please let me know if I need to provide any additional information. I have been stuck on this issue for close to two weeks and do not know where to go from here, I have exhausted almost all(if not all) online resources.

Final notes: I am using ESP-IDF 5.0.2 on VScode using the extention.
I could not get my main to upload but it is short so here it is(ui_init is the methos squareline gave me to display the keyboard etc):


void app_main(void)
{
/* Initialize I2C (for touch) */
bsp_i2c_init();

/* Initialize display and LVGL */
lv_disp_t * disp = bsp_display_start();

/* Turn on display backlight */
bsp_display_backlight_on();

app_lvgl_display();

ESP_LOGI(TAG, "Example initialization done.");
}
void app_lvgl_display(void)
{
bsp_display_lock(0);

ui_init();

bsp_display_unlock();
}


Here is the output from the monitor: I (24) boot: ESP-IDF v5.0.2 2nd stage bootloader
I (25) boot: compile time 11:41:41
I (25) boot: chip revision: v0.1
I (27) boot.esp32s3: Boot SPI Speed : 80MHz
I (31) boot.esp32s3: SPI Mode : DIO
I (36) boot.esp32s3: SPI Flash Size : 8MB
I (41) boot: Enabling RNG early entropy source...
I (46) boot: Partition Table:
I (50) boot: ## Label Usage Type ST Offset Length
I (57) boot: 0 nvs WiFi data 01 02 00009000 00004000
I (65) boot: 1 phy_init RF data 01 01 0000f000 00001000
I (72) boot: 2 factory factory app 00 00 00010000 00200000
I (80) boot: End of partition table
I (84) esp_image: segment 0: paddr=00010020 vaddr=3c050020 size=11df4h ( 73204) map
I (105) esp_image: segment 1: paddr=00021e1c vaddr=3fc93b00 size=02a1ch ( 10780) load
I (108) esp_image: segment 2: paddr=00024840 vaddr=40374000 size=0b7d8h ( 47064) load
I (121) esp_image: segment 3: paddr=00030020 vaddr=42000020 size=4ea88h (322184) map
I (180) esp_image: segment 4: paddr=0007eab0 vaddr=4037f7d8 size=042f8h ( 17144) load
I (190) boot: Loaded app from partition at offset 0x10000
I (190) boot: Disabling RNG early entropy source...
I (202) esp_psram: Found 2MB PSRAM device
I (202) esp_psram: Speed: 80MHz
I (248) mmu_psram: Instructions copied and mapped to SPIRAM
I (267) mmu_psram: Read only data copied and mapped to SPIRAM
I (267) cpu_start: Pro cpu up.
I (267) cpu_start: Starting app cpu, entry point is 0x40375484
0x40375484: call_start_cpu1 at C:/Users/Admin/Espressif/esp-idf/components/esp_system/port/cpu_start.c:141

I (0) cpu_start: App cpu up.
I (452) esp_psram: SPI SRAM memory test OK
I (461) cpu_start: Pro cpu start user code
I (461) cpu_start: cpu freq: 160000000 Hz
I (461) cpu_start: Application information:
I (464) cpu_start: Project name: s_p_7
I (469) cpu_start: App version: v5.0.2-dirty
I (474) cpu_start: Compile time: Jun 21 2023 17:27:14
I (480) cpu_start: ELF file SHA256: 80430d816ceb7716...
I (486) cpu_start: ESP-IDF: v5.0.2
I (491) cpu_start: Min chip rev: v0.0
I (496) cpu_start: Max chip rev: v0.99
I (501) cpu_start: Chip rev: v0.1
I (505) heap_init: Initializing. RAM available for dynamic allocation:
I (512) heap_init: At 3FC97498 len 00052278 (328 KiB): DRAM
I (519) heap_init: At 3FCE9710 len 00005724 (21 KiB): STACK/DRAM
I (525) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
I (532) heap_init: At 600FE010 len 00001FF0 (7 KiB): RTCRAM
I (538) esp_psram: Adding pool of 1600K of PSRAM memory to heap allocator
I (546) spi_flash: detected chip: gd
I (550) spi_flash: flash io: dio
W (554) spi_flash: Detected size(16384k) larger than the size in the binary image header(8192k). Using the size in the binary image header.
I (567) sleep: Configure to isolate all GPIO pins in sleep state
I (574) sleep: Enable automatic switching of GPIO sleep configuration
I (581) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
I (601) esp_psram: Reserving pool of 32K of internal memory for DMA/internal allocations
I (601) LVGL: Starting LVGL task
I (601) gpio: GPIO[45]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0
I (621) ESP32S3: Initialize Intel 8080 bus
I (621) ESP32S3: Install panel IO
I (631) ESP32S3: Install LCD driver of ili9488
I (631) ili9488: Configuring for RGB color order
I (641) ili9488: new ili9488 panel @0x3fca5934
I (641) ili9488: Sending SW_RESET to display
I (671) ili9488: Initializing ILI9488
I (871) ili9488: Initialization complete
I (971) ESP32S3: Turn on LCD backlight
After LCD |I (5981) ESP-EXAMPLE: Example initialization done.

[liyang5945]

your screen X coord is reversed，check your lcd_init code, every screen is different even if they use same driver IC

[muzgog]

Unfortunately that did not fix the issue. Still have random lines in the display and display not using the entire screen(when I have tried swapping both X and Y resolutions)