I've been trying to manually configure ESP32S3 registers on my custom PCB in order to set-up an I2C communication. The purpose is to get hands-on experience in writing device drivers and working with register fields/addresses.
I'm using ESP-IDF v5.1 with VS code.
In esp32-s3 Technical Reference Manual, this can be done by working inside I2C_CTR_REG register.
I selected I2C0 register whose base address is 0x60013000.
I've encountered two issues while trying to achieve this.
1st (Bonus) - The IO_MUX_n_REGISTER reset state is different from what is written in the TRM.
- IO_MUX_n_REG
- Screenshot 2023-04-25 at 16-47-18 esp32-s3_technical_reference_manual_en.pdf.png (24.05 KiB) Viewed 1059 times
Since I can write into this register, I will just clear the unwanted bits before setting the register field to my desired value. Still, if someone as any idea why there is a difference when I only am reading the register.
2nd - I can't write into I2C_CTR_REG.
As far as I understand it, the register can be accessed for reading and writing. However, the field value doesn't change. The field seems "locked". Is there an additional step to perform before trying to configure this register?
- I2C_CTR_REG
- Screenshot 2023-04-25 at 17-00-04 esp32-s3_technical_reference_manual_en.pdf.png (149.46 KiB) Viewed 1059 times
Code: Select all
int set_I2C_in_master_mode()
{
volatile uint32_t *address_of_I2C_control_register = (volatile uint32_t *) (I2C_CTR_REG);
printf("I2C Control Reg content before setting bits: 0x%08lX\n", *address_of_I2C_control_register);
*address_of_I2C_control_register = (*address_of_I2C_control_register) | (1 << I2C_MS_MODE_FIELD);
printf("I2C Control Reg content after setting bits: 0x%08lX\n", *address_of_I2C_control_register);
return(0);
}
int app_main()
{
set_I2C_in_master_mode();
return(0);
}
- --- idf_monitor on /dev/ttyACM0 115200 ---
- --- Quit: Ctrl+] | Menu: Ctrl+T | Help: Ctrl+T followed by Ctrl+H ---
- I (99) boot: 2 factory factory app 00 00 0ESP-ROM:esp32s3-20210327
- Build:Mar 27 2021
- rst:0x15 (USB_UART_CHIP_RESET),boot:0x2b (SPI_FAST_FLASH_BOOT)
- Saved PC:0x403783ce
- 0x403783ce: esp_cpu_wait_for_intr at /home/user/esp/esp-idf/components/esp_hw_support/cpu.c:121
- SPIWP:0xee
- mode:DIO, clock div:1
- load:0x3fce3818,len:0x16f4
- load:0x403c9700,len:0x4
- load:0x403c9704,len:0xc00
- load:0x403cc700,len:0x2eb0
- SHA-256 comparison failed:
- Calculated: a09bd1ec3e34ce03e0714dec31f74919e5988cd476f954f99420bebf61b3505c
- Expected: ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
- Attempting to boot anyway...
- entry 0x403c9908
- I (45) boot: ESP-IDF v5.1-dev-4557-gf404fe96b1 2nd stage bootloader
- I (45) boot: compile time Apr 25 2023 14:38:20
- I (46) boot: Multicore bootloader
- I (50) boot: chip revision: v0.1
- I (54) boot.esp32s3: Boot SPI Speed : 80MHz
- I (59) boot.esp32s3: SPI Mode : DIO
- I (63) boot.esp32s3: SPI Flash Size : 8MB
- I (68) boot: Enabling RNG early entropy source...
- I (73) boot: Partition Table:
- I (77) boot: ## Label Usage Type ST Offset Length
- I (84) boot: 0 nvs WiFi data 01 02 00009000 00006000
- I (92) boot: 1 phy_init RF data 01 01 0000f000 00001000
- I (99) boot: 2 factory factory app 00 00 00010000 00100000
- I (107) boot: End of partition table
- I (111) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=09cd8h ( 40152) map
- I (124) esp_image: segment 1: paddr=00019d00 vaddr=3fc91300 size=027f8h ( 10232) load
- I (129) esp_image: segment 2: paddr=0001c500 vaddr=40374000 size=03b18h ( 15128) load
- I (139) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=17780h ( 96128) map
- I (156) esp_image: segment 4: paddr=000377a8 vaddr=40377b18 size=097d4h ( 38868) load
- I (167) boot: Loaded app from partition at offset 0x10000
- I (168) boot: Disabling RNG early entropy source...
- I (179) cpu_start: Multicore app
- I (179) cpu_start: Pro cpu up.
- I (179) cpu_start: Starting app cpu, entry point is 0x4037523c
- 0x4037523c: call_start_cpu1 at /home/user/esp/esp-idf/components/esp_system/port/cpu_start.c:159
- I (0) cpu_start: App cpu up.
- I (198) cpu_start: Pro cpu start user code
- I (198) cpu_start: cpu freq: 160000000 Hz
- I (198) cpu_start: Application information:
- I (201) cpu_start: Project name: template-app
- I (206) cpu_start: App version: 1
- I (210) cpu_start: Compile time: Apr 25 2023 14:38:16
- I (217) cpu_start: ELF file SHA256: d19cfdc68d829505...
- I (223) cpu_start: ESP-IDF: v5.1-dev-4557-gf404fe96b1
- I (229) cpu_start: Min chip rev: v0.0
- I (234) cpu_start: Max chip rev: v0.99
- I (239) cpu_start: Chip rev: v0.1
- I (243) heap_init: Initializing. RAM available for dynamic allocation:
- I (251) heap_init: At 3FC94340 len 000553D0 (340 KiB): DRAM
- I (257) heap_init: At 3FCE9710 len 00005724 (21 KiB): STACK/DRAM
- I (263) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
- I (270) heap_init: At 600FE010 len 00001FF0 (7 KiB): RTCRAM
- I (277) spi_flash: detected chip: generic
- I (281) spi_flash: flash io: dio
- I (285) sleep: Configure to isolate all GPIO pins in sleep state
- I (291) sleep: Enable automatic switching of GPIO sleep configuration
- I (299) app_start: Starting scheduler on CPU0
- I (303) app_start: Starting scheduler on CPU1
- I (303) main_task: Started on CPU0
- I (313) main_task: Calling app_main()
- I2C Control Reg content before setting bits: 0x0000020B
- I2C Control Reg content after setting bits: 0x0000020B
- I (323) main_task: Returned from app_main()
Mike