Use SPICLK as GPIO15 on ESP32-C3

[vm__dm]

I am working on a custom board using the ESP32-C3FH4 (embedded flash) and I need to drive PIN22 (SPICLK) as a GPIO.
This should be assigned to GPIO15.
I use the following code to set it as a GPIO, output and high level.

Code: Select all

  const gpio_config_t gpio_config = {.pin_bit_mask = BIT(15),
                                          .mode = GPIO_MODE_OUTPUT,
                                          .pull_up_en = GPIO_PULLUP_DISABLE,
                                          .pull_down_en = GPIO_PULLDOWN_DISABLE,
                                          .intr_type = GPIO_INTR_DISABLE};
  gpio_config(&gpio_config);

  gpio_set_direction(GPIO_NUM_15, GPIO_MODE_OUTPUT);
  gpio_set_level(GPIO_NUM_15, 1);
  gpio_iomux_out(GPIO_NUM_15, FUNC_SPICLK_GPIO15, false);
  gpio_hold_dis(GPIO_NUM_15);

I do this configuration only once at the beginning of my app_main.
The app is configured for the right platform.
When I power-up my device I see that the pin is low and sometimes I see some activity on it that looks like an SPI clock (should be set at 40Mhz and I can't get a very clear signal).
Am I missing some steps in GPIO configuration for this specific pin?
I used the same code on ESP32-C3-devkit-1 (apart from the iomux call) on other pins that are GPIOs by default and had no issues.

[ESP_Sprite]

You cannot do that. As the datasheet indicates, that pin is used by the internal flash and should not be used.

[vm__dm]

I saw the note on chapter 3.4.1 of the DS, but that mentions the ESP32-C3FH4AZ variant and we currently use ESP32-C3FH4. There those pins are "not recommended", but we needed some very low-frequency outputs (resets of external devices that are set to a fixed state or toggled at boot) and since those pins have a GPIO alternate function we considered that usable.
Can you confirm that there's no way to drive those pins even on ESP32-C3FH4?
Is there an official document/errata about that?

[ESP_Sprite]

So technically those pins are usable, if you disable flash cache and poke them directly from IRAM (but you need to more-or-less stop execution of any other task while you have control over those IOs, outside of that they'll have the flash signals on them, so it's not an option for your use case), or disable the internal flash by tieing its CS high and relocating the flash pins to connect to a different set of GPIOs that connect to external flash; that's why all you get is the note in the datasheet.

In practice, they are unusable indeed.

[vm__dm]

Thanks a lot for the clarification.
Is this true for all the SPI interface signals, including WP, even if no external flash is connected?

[ESP_Sprite]

I would say so. WP still is connected to the internal flash (and generally used if you use QIO). Theoretically, with that pin in particular, you could conceivably get away with re-using it if you can set the configuration of the flash up to always ignore WP, and set up your IDF project to only use DIO to talk to the flash. (Same with HOLD; if you can convince the flash chip to ignore it and only use DIO, you could use that for something else.)