- Calibration fuses:
- BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0)
- ADC_VREF (BLOCK0): Voltage reference calibration = 1058 R/- (0b10110)
- Config fuses:
- XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0)
- XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0)
- XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0)
- CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 57 R/W (0x39)
- SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000)
- SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000)
- SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000)
- SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0b00000)
- SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000)
- DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0)
- Efuse fuses:
- WR_DIS (BLOCK0): Efuse write disable mask = 385 R/W (0x0181)
- RD_DIS (BLOCK0): Efuse read disable mask = 0 R/- (0x0)
- CODING_SCHEME (BLOCK0): Efuse variable block length scheme
- = NONE (BLK1-3 len=256 bits) R/W (0b00)
- KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0)
- Identity fuses:
- MAC (BLOCK0): Factory MAC Address
- = 7c:87:ce:f4:a1:78 (CRC 0x50 OK) R/W
- MAC_CRC (BLOCK0): CRC8 for factory MAC address = 80 R/W (0x50)
- CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1)
- CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = True R/W (0b1)
- CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10)
- CHIP_PACKAGE (BLOCK0): Chip package identifier = 1 R/W (0b001)
- MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00)
- Security fuses:
- FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 7 R/W (0b0000111)
- UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0)
- FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 15 R/W (0xf)
- CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1)
- ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0)
- ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = True R/W (0b1)
- JTAG_DISABLE (BLOCK0): Disable JTAG = True R/W (0b1)
- DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0)
- DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = True R/W (0b1)
- DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = True R/W (0b1)
Hello,
I have enabled the Secure boot V2 + flash encryption in my code.. I want to disable the flash encryption in EPS32. Can anyone provide the proper steps for Disable the Flash encryption?
Thanks In Advance,
Jainam Shah