DAC frequency limitations; use of APLL

[hpeteranvin]

Hi,

I wonder if anyone has any idea of what the practical frequency limits of the built-in DAC happens to be.
Also, the TDM states that when used in DAC mode one should use PLL_D2_CLK as the reference, but the top says that when using PLL_D2_CLK as a reference one should avoid fractional divisors. Are either of these negotiable?

[ESP_Sprite]

I don't think there's a hard limit to the DAC frequency... I do know I've gotten a good 13MHz or so out of it, although I can't comment on the specifics wrt noise figures. Wrt trm: My guess is that you should avoid fractional divisors as they introduce jitter in the sampling rate, and you're better off just configuring the PLL for the rate you want instead.

[hpeteranvin]

OK, so I am guessing you are telling me to use the APLL after all?
At that frequency it has a *lot* of potential.