WROOM-32 (DevKitC) QIO/40MHz operation keeps resetting
Posted: Wed Jan 18, 2017 2:35 am
I tried to configure QIO/40MHz operation (using menuconfig), and I see the following on UART0-console:
Is this a known issue?
Programming the image using 'make flahsh' is ok.
DIO mode it operates correctly.
My build environment is Windows 10 host running MSYS2 (from esp32_win32_msys2_environment_and_toolcahin-20170111.zip)
and esp-idf sync from 1/15/2017
Also, I would like to run QSPI flash at 80MHz on DevKitC. Is that supported?
Code: Select all
ets Jun 8 2016 00:22:57
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
flash read err, 1000
Falling back to built-in command interpreter.
OK
>ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x3fff0008,len:8
load:0xffffffff,len:-1
ets Jun 8 2016 00:22:57
rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:QIO, clock div:2
load:0x3fff0008,len:8
load:0xffffffff,len:-1
Programming the image using 'make flahsh' is ok.
DIO mode it operates correctly.
Code: Select all
ets Jun 8 2016 00:22:57
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0x00
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0008,len:8
load:0x3fff0010,len:3384
load:0x40078000,len:7452
ho 0 tail 12 room 4
load:0x40080000,len:252
entry 0x40080034
I (46) boot: ESP-IDF v1.0-387-gca9f62a 2nd stage bootloader
and esp-idf sync from 1/15/2017
Also, I would like to run QSPI flash at 80MHz on DevKitC. Is that supported?