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IO0 Internal Pullup Disabled? [IDFGH-4504]
Posted: Sat Feb 23, 2019 1:10 pm
by nebkat
I have designed my own board for ESP32-WROOM-32D but I'm having issues with boot mode selection. It seems that the internal pullup of IO0 is not working, as it boots to download mode by default. Checking the voltage at boot it is indeed at 0V rather than high. After connecting a 10k resistor to 3V3 it boots fine. Before this, IO0 was left unconnected.
As far as I know IO0 is not required to have an external pullup, and it doesn't have one on the DevKitC. Could it be possible that the internal pullup had been disabled or damaged?
Re: IO0 Internal Pullup Disabled?
Posted: Tue Feb 26, 2019 10:30 pm
by DurandA
I got the exact same problem. I just soldered a new revision of a board I am developing and it goes to download mode without a pullup resistor. I did not have this problem with older chips.
Re: IO0 Internal Pullup Disabled?
Posted: Wed Feb 27, 2019 12:01 am
by ESP_Angus
I don't know, but it's possible the internal pullup is not strong enough on all chips. I'll ask the hardware team to check on this and get back to you.
Re: IO0 Internal Pullup Disabled?
Posted: Wed Feb 27, 2019 9:52 am
by ESP_Stone
Will you guys please post your schematic here? Thanks.
Re: IO0 Internal Pullup Disabled?
Posted: Wed Feb 27, 2019 7:56 pm
by DurandA
Here you are:
Please note that IO0 is wired to a ISP header, but IO0 is left unconnected in the header.
Re: IO0 Internal Pullup Disabled?
Posted: Thu Feb 28, 2019 2:02 am
by ESP_Stone
I suggest you add one 1uF cap close to ENABLE. Like below showed:
Re: IO0 Internal Pullup Disabled?
Posted: Thu Feb 28, 2019 2:05 am
by ESP_Stone
Sorry, add the picture.
Re: IO0 Internal Pullup Disabled?
Posted: Thu Feb 28, 2019 2:22 am
by DurandA
C5 of 1uF is placed very close to ENABLE. However, I do not have that R2 resistor. I guess its purpose is to isolate the analog ground from the digital ground.
- Screenshot_2019-02-28 EasyEDA - A Simple and Powerful Electronic Circuit Design Tool.png (103.9 KiB) Viewed 14207 times
Re: IO0 Internal Pullup Disabled?
Posted: Thu Feb 28, 2019 10:13 am
by ESP_Sprite
You actually do have the equivalent of R2 in the schematic; it's R6 on your PCB. What you do not have is an 1uF cap from EN to GND. C5 on your PCB is a decoupling cap, the same as C2 in Stone's schematic.
Re: IO0 Internal Pullup Disabled?
Posted: Thu Feb 28, 2019 1:08 pm
by DurandA
Thanks @ESP_Stone and @ESP_Sprite, it seems I was very tired when reading this. Indeed, this capacitor is part of Figure 4: ESP32-WROOM-32 Peripheral Schematics from ESP32-WROOM-32 datasheet and I somehow missed it.
I will solder an extra capacitor and report back. Let's see if @nebkat issue is related to mine.